Silicon carbide (SiC) devices offer significantly faster switching speeds than traditional silicon devices, thereby improving motor drive efficiency. However, these high switching speeds can exacerbate voltage reflection issues, especially when the motor is connected via long cables. Although driving parameters are often tuned to address this, existing techniques struggle to balance effective voltage suppression with acceptable switching losses. This paper proposes an approach to simultaneously mitigate voltage reflection and reduce switching losses through optimized driving circuit design. Specifically, it analyzes the effects of key parameters: gate resistance and external Miller capacitance on voltage behavior and energy loss. A detailed model is developed to characterize both the voltage reflection process and the switching dynamics of SiC MOSFETs in a single phase-leg configuration. Based on this model, the study quantifies how voltage transition time and switching loss evolve under various drive conditions. Furthermore, a Pareto front-based optimization method is introduced to balance the trade-off between voltage slew rate and switching efficiency. Experimental validation on a 1.2 kW SiC-based motor drive shows that voltage overshoot can be reduced from 83.3% to 63.3% by optimizing the gate resistor, while adding an external Miller capacitor further reduces it to 23.3%, a 40% improvement over resistor adjustment alone, with only a 0.06% efficiency penalty.