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Queue locks on cache coherent multiprocessors
RISE - Research Institutes of Sweden (2017-2019), ICT, SICS.
RISE - Research Institutes of Sweden (2017-2019), ICT, SICS.
Sun Microsystems, United States.
1994 (English)Conference paper, Published paper (Refereed)
Abstract [en]

Large-scale shared-memory multiprocessors typically have long latencies for remote data accesses. A key issue for execution performance of many common applications is the synchronization cost. The communication scalability of synchronization has been improved by the introduction of queue-based spm-locks instead of Test&(Test&Set). For architectures with long access latencies for global data, attention should also be paid to the number of global accesses that arc involved in synchronization. We present a method to characterize the performance of proposed queue lock algorithms, and apply it to previously published algorithms. We also present two new queue locks, the LH lock and the M lock. We compare the locks tn terms of performance, memory requirements, code size, and required hardware support. The LH lock is the simplest of all the locks, yet requires only an atomic swap operation. The M lock is superior in terms of global accesses needed to perform synchronization and still competitive tn all other criteria. We conclude that the M lock is the best overall queue lock for the class of architectures studied. 

Place, publisher, year, edition, pages
1994, 1.
National Category
Computer and Information Sciences
Identifiers
URN: urn:nbn:se:ri:diva-22862DOI: 10.1109/ipps.1994.288305Scopus ID: 2-s2.0-105047337020OAI: oai:DiVA.org:ri-22862DiVA, id: diva2:1042427
Conference
8th International Parallel Processing Symposium (IPPS), April 1994, Cancún, Mexico
Note

Funding textWe'd like to thank the SICS sponsors for their continued support: ABB, Swedish Defense Material Administration, IBM Sweden, CelsiusTech, Ericsson, and Telia.

Available from: 2016-10-31 Created: 2016-10-31 Last updated: 2026-09-04Bibliographically approved

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