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Run-time mapping algorithm for dynamic workloads on heterogeneous MPSoCs platforms
University of Tehran, Iran.ORCID-id: 0000-0001-5951-9374
University of Tehran, Iran.
2018 (engelsk)Inngår i: Proceedings - 21st Euromicro Conference on Digital System Design, DSD 2018, s. 373-380Artikkel i tidsskrift (Fagfellevurdert) Published
Abstract [en]

Task mapping exploration plays an important role in the high performance achieved by heterogeneous multi-processor system-on-chip (MPSoC) platforms. The dynamic of application workloads in modern MPSoC-based embedded systems are consistently growing. Nowadays, the execution of different applications is done concurrently and these applications compete for resources in such systems. This paper presents a novel run-time mapping algorithm for multimedia applications. The objective of application mapping is to minimize execution time in a predefined budget of energy consumption. This algorithm is divided to two phases: design-time and run-time. During design-time, application clustering is combined with design space exploration, then a set of rules for mapping is extracted by using Association Rule Mining techniques, and after that, during run-time, feature extraction and application classification is performed based on the rule sets. The evaluation of the proposed algorithm is done by using a heterogeneous MPSoC system with several applications that have different communication and computation behaviors. The experimental results revealed that during run-time, applications were correctly classified by the proposed algorithm and the best resources selected for mapping accurately. The results clearly showcase the proposed algorithm’s effectiveness. 

sted, utgiver, år, opplag, sider
Institute of Electrical and Electronics Engineers Inc. , 2018. s. 373-380
Emneord [en]
Budget control; Conformal mapping; Embedded systems; Energy utilization; Multiprocessing systems; System-on-chip; Systems analysis, Application classifications; Association mining; Design space exploration; Heterogeneous mpsoc; Multi processor system on chips; Multimedia applications; Rule mining techniques; Run-time mapping, Integrated circuit design
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Identifikatorer
URN: urn:nbn:se:ri:diva-67480DOI: 10.1109/DSD.2018.00071Scopus ID: 2-s2.0-85056453754OAI: oai:DiVA.org:ri-67480DiVA, id: diva2:1802968
Tilgjengelig fra: 2023-10-06 Laget: 2023-10-06 Sist oppdatert: 2025-09-23bibliografisk kontrollert

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