Building on many discoveries and inventions, electronics started affecting people's everyday lives in a significant fashion following the invention of the first solid-state transistor in the late 1940s. The miniaturization paved way for the mass electronics production and later the digital revolution, the outcomes of which are visible to all members of the public today. After about a two-decade-long swing around 2000s from hardware towards software regarding what affects lives more, a point has now been reached where electronics is more important to all and its use is more ubiquitous and crucial than ever before. In most if not all end user or industrial applications, the capability and quality of electronics hardware are the key determining factors. The European electronics components and systems (ECS) industry has traditionally had a high base line for electronics innovation. However, the industry is now compelled, partly due to competition and partly due to customer demand, to manufacture even more reliable electronics products than before. Guaranteeing the reliability of electronics hardware entails the entire ECS value chain to undergo a paradigm shift to holistically address reliability as a key issue. The European ECS industry previously adopted overseas outsourcing considerably, however it is now taking steps to reshape itself into a more coherent value chain with the aim of having not only the electronics designs but also the electronics manufacturing made in Europe. The H2020-ECSEL program successfully funds highly competitive projects in the area of electronics components and systems. We present here the almost final results of a similarly funded project entitled Intelligent Reliability 4.0 (“iRel40”), by providing a background to the topic of ECS, project objectives, the methodologies we have followed, and the results we have obtained during the first 36 months of this ongoing project

The availability of data and AI-based methods have in recent years advanced the field of prognostics and health management. However, making accurate predictions of Remaining Useful Life (RUL) on products being used in operational environments, based on lifetime models from accelerated ageing experiments in the lab, is not straightforward. This paper introduces a recently patented method [1] for correlating lab-measured accumulated damage – gathered through accelerated aging experiments – with the RUL of products in the field, specifically with respect to the degradation mechanisms observed during testing. The method bridges the gap between prediction models developed from datasets recorded in a lab, to datasets available in the field. The method is based on the following steps: (i) mapping of the degradation process, (ii) exposure of samples to different levels of degradation, (iii) insertion of degraded samples in the final products, (iv) measurement of product-level responses to the different levels of degradation, and (v) comparison of those degradation responses to data from products in the field. One example of a degradation mechanism (wire bond lift-off) in power semiconductor packages is used to illustrate the method. However, the method is technology agnostic and can generally also be used for batteries, electric motors, or any application where a degradation can, with good accuracy, be modelled in the lab.

High-density electronics packaging requires fabrication of intricate conductive and dielectric features within a dense three-dimensional structure. Simultaneous deposition of both conductive and insulative printing materials using multimaterial additive manufacturing (AM) provides new opportunities to fabricate electronics packages with complex designs. This article reports the first demonstration of fully printed power die-embedded electronics package for wide band-gap devices. For this purpose, multimaterial inkjet AM was used to print a 0.5-mm thick electronics package for gallium nitride (GaN) power chips. The conductive parts of the package, including traces and vias, were printed using a high electrical conductivity silver ink, while a polyimide ink was used to print dielectric parts. The electrical characterization tests showed the reasonable performance of the printed package. While the conventional embedded packaging includes many steps such as laminating, plating, and drilling, which creates significant material waste and environmental issues, the proposed AM approach is done in a single step without material waste. 

To generate data used for developing schemes and models for CM, PHM, and for estimating RUL of power electronic devices, accelerated aging experiments in the form of power cycling are often performed. In these experiments, a set current is passed through the power devices and is turned on and off in regular cycles. Due to the mismatch in CTEs of the materials in the devices, the on/off cycles will generate thermally induced stress in the various material interfaces, which is the main cause of failures. Most of the power cycling setups that are currently used can only manage a single set on-state current level and fixed on/off times (which is also the common standard for lifetime testing); a condition that is very far from most real applications. The experimental setup described here is based on a Gamry Reference 3000AEpotentiostat/galvanostat/ZRA working with a Gamry 30k Booster, which can be programmed to generate a variable load current profile and will thus enable the application of more realistic conditions for accelerated aging of power electronic devices in the lab. This will improve prognostics model development and provide excellent use cases for evaluating the capabilities of the prognostics algorithms for generalization to field conditions. The application of variable load profiles from the field, instead of the regular on/off cycles traditionally used, is not compatible with the commonly used method of using the chip itself as a temperature sensor. Instead, we here present a novel method of estimating the junction temperature using a device specific derivation of thermal parameters from the measured cooling block temperature, case temperature, and dissipated power in conjunction with simulations using the PySpice simulation package implemented in Python. The setup coupled with the new junction temperature estimation is an important step in enabling predictive maintenance of power devices that is currently missing from the power electronics community. © 2024 IEEE.

Double sided modules accommodating wide band gap (WBG) devices are increasingly used in electric vehicles owing to their lower thermal resistance and parasitic inductances. Compared with single sided modules having a single ceramic substrate, the mechanical constraint applied on the silver sintered bonding layers in double sided modules (with two ceramic substrates) poses a more challenging reliability issue. In this work, we develop a parametric model to investigate the effects of layout, geometry and material properties on damage distribution in silver sintered layers of double sided modules. Anand viscoplastic model was used to describe the inelastic deformation of sintered silver under power cycling. Equivalent inelastic strain accumulated in each power cycle was used as the damage parameter and failure criterion. The model enables parametric study of damage distribution in double sided modules, and help improve design for maximum reliability. Using this model, the effects of parameters such as spacer and die thicknesses were investigated in this study.

Robust and accurate prognostics models for estimation of remaining useful life (RUL) are becoming an increasingly important aspect of research in reliability and safety in modern electronic components and systems. In this work, a data driven approach to the prognostics problem is presented. In particular, machine learning models are trained to predict the RUL of wire-bonded silicon carbide (SiC) metal-oxide-semiconductor field-effect transistors (MOSFETs) subjected to power cycling until failure. During such power cycling, ON-state voltage and various temperature measurements are continuously collected. As the data set contains full run-to-failure trajectories, the issue of estimating RUL is naturally formulated in terms of supervised learning. Three neural network architectures were trained, evaluated, and compared on the RUL problem: a temporal convolutional neural network (TCN), a long short-term memory neural network (LSTM) and a convolutional gated recurrent neural network (Conv-GRU). While the results show that all networks perform well on held out testing data if the testing samples are of similar aging acceleration as the samples in the training data set, performance on out-of-distribution data is significantly lower. To this end, we discuss potential research directions to improve model performance in such scenarios.

Residual stresses created during the packaging process can adversely affect the reliability of electronics components. We used incremental hole-drilling method, following the ASTM E 837-20 standard, to measure packaging induced residual stresses in discrete packages of power electronics components. For this purpose, we bonded a strain gauge on the surface of a Gallium Nitride (GaN) power component, drilled a hole through the thickness of the component in several incremental steps, recorded the relaxed strain data on the sample surface using the strain gauge, and finally calculated the residual stresses from the measured strain data. The recorded strains and the residual stresses are related by the compliance coefficients. For the hole drilling method in the isotropic materials, the compliance coefficients are calculated from the analytical solutions, and available in the ASTM standard. But for the orthotropic multilayered components typically found in microelectronics assemblies, numerical solutions are necessary. We developed a subroutine in ANSYS APDL to calculate the compliance coefficients of the hole drilling test in the molded and embedded power electronics components. This can extend the capability of the hole drilling method to determine residual stresses in more complex layered structures found in electronics. 

Recording and prediction of the accumulated damage, which will eventually lead to the failure of power electronic modules, is an aspect of high importance for power electronic systems design and, in particular, for development of Prognostic and Health Management (PHM) schemes for in-field applications. To this end, this paper presents a simple and cost-effective prognostic method for predicting the remaining useful life (RUL) of TO-247 packaged silicon carbide (SiC) metal-oxide semiconductor field-effect transistors (MOSFETs) subjected to power cycling experiments. The model assumes that the major failure mode is bond-wire lift-off and uses a damage accumulation scheme based on Paris’ crack law. The only inputs to the model are historical data on the average junction temperature swing and the temperaturecompensated drain-source ON-state resistance at the peak temperature of the current cycle. Using only these two input values, the model is shown to predict RUL with surprising accuracy for the range of constant current loads determining cycling conditions under which the test data series have been acquired. This work is a first step in an ongoing project towards building more elaborate prognostic schemes for RUL-determination of SiC power MOSFETs in actual working conditions, using physics-informed neural networks (PINNs).

Compared with silicon-based power devices, wide band gap (WBG) semiconductor devices operate at significantly higher power densities required in applications such as electric vehicles and more electric airplanes. This necessitates development of power electronics packages with enhanced thermal characteristics that fulfil the electrical insulation requirements. The present research investigates the feasibility of using ceramic additive manufacturing (AM), also known as three-dimensional (3D) printing, to address thermal and electrical requirements in packaging gallium nitride (GaN) based high-electron-mobility transistors (HEMTs). The goal is to exploit design freedom and manufacturing flexibility provided by ceramic AM to fabricate power device packages with a lower junction-to-ambient thermal resistance (<italic>R</italic>&#x03B8;JA). Ceramic AM also enables incorporation of intricate 3D features into the package structure in order to control the isolation distance between the package source and drain contact pads. Moreover, AM allows to fabricate different parts of the packaging assembly as a single structure to avoid high thermal resistance interfaces. For example, the ceramic package and the ceramic heatsink can be printed as a single part without any bonding layer. Thermal simulations under different thermal loading and cooling conditions show the improvement of thermal performance of the package fabricated by ceramic AM. If assisted by an efficient cooling strategy, the proposed package has the potential to reduce <italic>R</italic>&#x03B8;JA by up to 48%. The results of the preliminary efforts to fabricate the ceramic package by AM are presented, and the challenges that have to be overcome for further development of this manufacturing method are recognized and discussed. 

Silicon carbide (SiC) power devices are steadily increasing their market share in various power electronics applications. However, they require low-inductive packaging in order to realize their full potential. In this research, low-inductive layouts for half-bridge power modules, using a direct bonded copper (DBC) substrate, that are suitable for SiC power devices, were designed and tested. To reduce the negative effects of the switching transients on the gate voltage, flexible printed circuit boards (PCBs) were used to interconnect the gate and source pins of the module with the corresponding pads of the power chips. In addition, conductive springs were used as low inductive, solder-free contacts for the module power terminals. The module casing and lid were produced using additive manufacturing, also known as 3D printing, to create a compact design. It is shown that the inductance of this module is significantly lower than the commercially available modules.