When PCBs in electronics assemblies absorb moisture in humid environments, a swelling hygroscopic stress is developed in the PCB. The induced swelling stresses cause the PCB to deform and expand in volume, and may adversely affect the connected solder joints, and limit their lifetime. We developed a non-linear finite element analysis to investigate the effect of PCB moisture absorption and swelling on damage accumulation in BGA solder joints of a ceramic component. For this purpose, moisture diffusion in PCB was modelled by Fick's law, which enables calculation of moisture concentration and the resulting deformation in PCB. The solder joints attaching the component to the PCB are affected by PCB deformation, and may develop inelastic stresses and strains. A viscoplastic material model was used to represent solder inelastic behaviour, and capture its damage evolution. The effect of PCB thickness on the solder maximum stress was also studied. The simulation results provide a framework to investigate the effect of humid environments on solder joints reliability

The availability of data and AI-based methods have in recent years advanced the field of prognostics and health management. However, making accurate predictions of Remaining Useful Life (RUL) on products being used in operational environments, based on lifetime models from accelerated ageing experiments in the lab, is not straightforward. This paper introduces a recently patented method [1] for correlating lab-measured accumulated damage – gathered through accelerated aging experiments – with the RUL of products in the field, specifically with respect to the degradation mechanisms observed during testing. The method bridges the gap between prediction models developed from datasets recorded in a lab, to datasets available in the field. The method is based on the following steps: (i) mapping of the degradation process, (ii) exposure of samples to different levels of degradation, (iii) insertion of degraded samples in the final products, (iv) measurement of product-level responses to the different levels of degradation, and (v) comparison of those degradation responses to data from products in the field. One example of a degradation mechanism (wire bond lift-off) in power semiconductor packages is used to illustrate the method. However, the method is technology agnostic and can generally also be used for batteries, electric motors, or any application where a degradation can, with good accuracy, be modelled in the lab.

High-density electronics packaging requires fabrication of intricate conductive and dielectric features within a dense three-dimensional structure. Simultaneous deposition of both conductive and insulative printing materials using multimaterial additive manufacturing (AM) provides new opportunities to fabricate electronics packages with complex designs. This article reports the first demonstration of fully printed power die-embedded electronics package for wide band-gap devices. For this purpose, multimaterial inkjet AM was used to print a 0.5-mm thick electronics package for gallium nitride (GaN) power chips. The conductive parts of the package, including traces and vias, were printed using a high electrical conductivity silver ink, while a polyimide ink was used to print dielectric parts. The electrical characterization tests showed the reasonable performance of the printed package. While the conventional embedded packaging includes many steps such as laminating, plating, and drilling, which creates significant material waste and environmental issues, the proposed AM approach is done in a single step without material waste. 

Graphene layers have a very high basal plane thermal conductivity, but a low conductivity out-of-plane. When placed on a heat source, they can efficiently spread heat laterally, but not vertically. To fully exploit ultrahigh basal plane thermal conductivity of graphene layers, they can be assembled vertically. We examine the efficiency of vertically aligned graphene layers as thermal interface material (TIM) for gallium nitride (GaN) high electrons mobility transistors (HEMTs) with ceramic packages. The junction temperature (Tj) is directly measured using thermocouples bonded to the die. The measurements are done under free convection in the ambient. The graphene results are compared with two conventional TIMs. It is shown the graphene TIM can lower the Tj by at least 5 °C. More temperature reduction is expected when testing with forced cooling. A transient thermal finite element model is also used for temperature prediction, showing good agreement with the experimental data.

To generate data used for developing schemes and models for CM, PHM, and for estimating RUL of power electronic devices, accelerated aging experiments in the form of power cycling are often performed. In these experiments, a set current is passed through the power devices and is turned on and off in regular cycles. Due to the mismatch in CTEs of the materials in the devices, the on/off cycles will generate thermally induced stress in the various material interfaces, which is the main cause of failures. Most of the power cycling setups that are currently used can only manage a single set on-state current level and fixed on/off times (which is also the common standard for lifetime testing); a condition that is very far from most real applications. The experimental setup described here is based on a Gamry Reference 3000AEpotentiostat/galvanostat/ZRA working with a Gamry 30k Booster, which can be programmed to generate a variable load current profile and will thus enable the application of more realistic conditions for accelerated aging of power electronic devices in the lab. This will improve prognostics model development and provide excellent use cases for evaluating the capabilities of the prognostics algorithms for generalization to field conditions. The application of variable load profiles from the field, instead of the regular on/off cycles traditionally used, is not compatible with the commonly used method of using the chip itself as a temperature sensor. Instead, we here present a novel method of estimating the junction temperature using a device specific derivation of thermal parameters from the measured cooling block temperature, case temperature, and dissipated power in conjunction with simulations using the PySpice simulation package implemented in Python. The setup coupled with the new junction temperature estimation is an important step in enabling predictive maintenance of power devices that is currently missing from the power electronics community. © 2024 IEEE.

Remaining useful life prediction models are a central aspect of developing modern and capable prognostics and health management systems. Recently, such models are increasingly data-driven and based on various machine learning techniques, in particular deep neural networks. Such models are notoriously “data hungry”, i.e., to get adequate performance of such models, a substantial amount of diverse training data is needed. However, in several domains in which one would like to deploy data-driven remaining useful life models, there is a lack of data or data are distributed among several actors. Often these actors, for various reasons, cannot share data among themselves. In this paper a method for collaborative training of remaining useful life models based on federated learning is presented. In this setting, actors do not need to share locally held secret data, only model updates. Model updates are aggregated by a central server, and subsequently sent back to each of the clients, until convergence. There are numerous strategies for aggregating clients’ model updates and in this paper two strategies will be explored: 1) federated averaging and 2) federated learning with personalization layers. Federated averaging is the common baseline federated learning strategy where the clients’ models are averaged by the central server to update the global model. Federated averaging has been shown to have a limited ability to deal with non-identically and independently distributed data. To mitigate this problem, federated learning with personalization layers, a strategy similar to federated averaging but where each client is allowed to append custom layers to their local model, is explored. The two federated learning strategies will be evaluated on two datasets: 1) run-to-failure trajectories from power cycling of silicon-carbide metal-oxide semiconductor field-effect transistors, and 2) C-MAPSS, a well-known simulated dataset of turbofan jet engines. Two neural network model architectures commonly used in remaining useful life prediction, long short-term memory with multi-layer perceptron feature extractors, and convolutional gated recurrent unit, will be used for the evaluation. It is shown that similar or better performance is achieved when using federated learning compared to when the model is only trained on local data.

Residual stresses created during the packaging process can adversely affect the reliability of electronics components. We used incremental hole-drilling method, following the ASTM E 837-20 standard, to measure packaging induced residual stresses in discrete packages of power electronics components. For this purpose, we bonded a strain gauge on the surface of a Gallium Nitride (GaN) power component, drilled a hole through the thickness of the component in several incremental steps, recorded the relaxed strain data on the sample surface using the strain gauge, and finally calculated the residual stresses from the measured strain data. The recorded strains and the residual stresses are related by the compliance coefficients. For the hole drilling method in the isotropic materials, the compliance coefficients are calculated from the analytical solutions, and available in the ASTM standard. But for the orthotropic multilayered components typically found in microelectronics assemblies, numerical solutions are necessary. We developed a subroutine in ANSYS APDL to calculate the compliance coefficients of the hole drilling test in the molded and embedded power electronics components. This can extend the capability of the hole drilling method to determine residual stresses in more complex layered structures found in electronics. 

Compared with silicon-based power devices, wide band gap (WBG) semiconductor devices operate at significantly higher power densities required in applications such as electric vehicles and more electric airplanes. This necessitates development of power electronics packages with enhanced thermal characteristics that fulfil the electrical insulation requirements. The present research investigates the feasibility of using ceramic additive manufacturing (AM), also known as three-dimensional (3D) printing, to address thermal and electrical requirements in packaging gallium nitride (GaN) based high-electron-mobility transistors (HEMTs). The goal is to exploit design freedom and manufacturing flexibility provided by ceramic AM to fabricate power device packages with a lower junction-to-ambient thermal resistance (<italic>R</italic>&#x03B8;JA). Ceramic AM also enables incorporation of intricate 3D features into the package structure in order to control the isolation distance between the package source and drain contact pads. Moreover, AM allows to fabricate different parts of the packaging assembly as a single structure to avoid high thermal resistance interfaces. For example, the ceramic package and the ceramic heatsink can be printed as a single part without any bonding layer. Thermal simulations under different thermal loading and cooling conditions show the improvement of thermal performance of the package fabricated by ceramic AM. If assisted by an efficient cooling strategy, the proposed package has the potential to reduce <italic>R</italic>&#x03B8;JA by up to 48%. The results of the preliminary efforts to fabricate the ceramic package by AM are presented, and the challenges that have to be overcome for further development of this manufacturing method are recognized and discussed. 

Silicon carbide (SiC) power devices are steadily increasing their market share in various power electronics applications. However, they require low-inductive packaging in order to realize their full potential. In this research, low-inductive layouts for half-bridge power modules, using a direct bonded copper (DBC) substrate, that are suitable for SiC power devices, were designed and tested. To reduce the negative effects of the switching transients on the gate voltage, flexible printed circuit boards (PCBs) were used to interconnect the gate and source pins of the module with the corresponding pads of the power chips. In addition, conductive springs were used as low inductive, solder-free contacts for the module power terminals. The module casing and lid were produced using additive manufacturing, also known as 3D printing, to create a compact design. It is shown that the inductance of this module is significantly lower than the commercially available modules.

Den brist på halvledare som industrin upplevt under 2021 har satt den annars tämligen anonyma halvledarindustrin i rampljuset såväl i Sverige som i Europa, USA och globalt. Hur länge denna brist kommer att bestå är en viktig fråga för industrin, som dock är svår att svara på. Enligt internationella analytiker kommer industrin att uppleva halvledarbrist fram till sommaren 2022 och eventuellt in på nästa höst eller eventuellt längre, varefter det föreligger en risk för överproduktion då lager förmodligen byggts upp bland avnämare. Erfarenheterna från tidigare halvledarbrister är att de så småningom övergår i överskott. Men den nuvarande bristen kan sannolikt kräva längre tid för detta än tidigare brister. Främsta skälet är att de halvledarfabriker som för närvarande är under uppbyggnad för att råda bot på bristen lider av samma överhettade försörjningskedjor som övrig industri, med förseningar av allt från vitala utrustningar till förbrukningsmateriel, och att det därför troligen kommer att ta längre tid än planerat att få dem i drift. Detta kan i värsta fall innebära att det rentav kan ta ett eller flera år längre tid än analytikerna förutspått innan försörjningsläget är normalt. Sverige är en del av det globala halvledarekosystemet – ett komplext ekosystem som kännetecknas av hög grad av arbetsfördelning, hög kapitalintensitet, hög kunskapsintensitet, långa produktionstider, stark internationalisering och starka inlåsningseffekter. Sverige interagerar med detta globala ekosystem på två sätt - som leverantör av produkter och tjänster i ett antal nischer där vi uppvisar global spetskompetens samt som avnämare av halvledarprodukter för industriella behov. Båda dessa sidor behöver stärkas för att a) våra SMF och stora företag ska kunna få tillgång till de halvledare och system byggda på halvledare som krävs för den produktion av produkter och tjänster som bidrar till Sveriges välstånd, b) svenska industriföretag ska kunna säkra tillgång till den kompetens och de tjänster som krävs då industrins produkter innehåller allt större mängd halvledare, och c) för att maximera möjligheterna för svenska halvledar- och elektronikinnovationer att hävda sig på världsmarknaden, och på så sätt bidra till landets välstånd. Det övergripande målet för Sverige bör vara att använda vår nationella styrka inom innovation som hävstång, och fokusera de starka specialiserade kompetenserna som finns här i landet, jämte långsiktiga investeringar i forskning inom halvledarteknik, systemdesign och halvledarmaterial, i syfte att med samlad kraft nå följande strategiska mål: 1) Etablera Sverige som ett halvledarinnovationsland genom att stärka vårt innovationssystem för halvledare och halvledarmaterial. 2) Få utväxling på de svenska investeringarna i forsknings- och innovationsinfrastruktur för design och produktion av halvledare. 3) Säkra och vidmakthåll en roll för Sverige i halvledarindustrin, inte minst genom svensk representation i de organ och församlingar som beslutar om framtida europeiska investeringar. För att nå dessa mål krävs stark samverkan mellan industri, akademi, institut och offentlig sektor, och långsiktiga såväl publika som privata investeringar i utbildning, forskningsinfrastruktur, test- och demonstrationsanläggningar och i startup- och scaleup-bolag. RISE åsikt är att Sverige därtill bör ta aktiv del i EU-initiativ som den europeiska halvledaralliansen (Alliance on Processor and Semiconductor Technologies) och European Chips Act. Påpekas bör att dessa mål är långsiktiga och kräver kontinuerligt arbete och finansiering under många år framöver. De löser inte industrins kortsiktiga behov av halvledare, och det kommer att ta tid att säkra industrins behov av halvledarkompetens. Med en väl genomförd strategi skulle dock dessa behov i högre grad kunna tillgodoses samtidigt som vårt lands bidrag till det globala halvledarekosystemet skulle växa kraftigt, till fromma för vårt gemensamma välstånd.