The paper presents a comparative analysis between a single side cooled (SSC) power module (PM) and two double side cooled (DSC) PMs - a flip-chip and a non-flip-chip arrangements. These three PM layouts are compared in terms of footprint size, parasitic capacitance, stray inductance, thermal impedance, switching performance, and power loss under the same conditions. The results indicate that the SSC PM has the lowest parasitic capacitance and inductance, whereas the flip-chip DSC PM has the highest power density (smallest footprint), and despite that it has the lowest thermal impedance. Overall, the non-flip-chip DSC PM has the least favorable characteristics among the three layouts.

High-density electronics packaging requires fabrication of intricate conductive and dielectric features within a dense three-dimensional structure. Simultaneous deposition of both conductive and insulative printing materials using multimaterial additive manufacturing (AM) provides new opportunities to fabricate electronics packages with complex designs. This article reports the first demonstration of fully printed power die-embedded electronics package for wide band-gap devices. For this purpose, multimaterial inkjet AM was used to print a 0.5-mm thick electronics package for gallium nitride (GaN) power chips. The conductive parts of the package, including traces and vias, were printed using a high electrical conductivity silver ink, while a polyimide ink was used to print dielectric parts. The electrical characterization tests showed the reasonable performance of the printed package. While the conventional embedded packaging includes many steps such as laminating, plating, and drilling, which creates significant material waste and environmental issues, the proposed AM approach is done in a single step without material waste. 

Junction termination design has become a crucial process in ultrahigh-voltage 4H-SiC device design since it enhances the reliability and ensures that the device can reach the designed breakdown voltage. In this work, we review the blocking performances, fabrication considerations and area efficiencies of several typical termination structures widely used for ultrahigh-voltage 4H-SiC devices, and aim to optimize the termination design of next generation devices, focusing on improved termination efficiency, simultaneous design of breakdown voltage and surface field without introducing extra fabrication complexity and costs. The relationship between area efficiency, surface electric field and breakdown voltage is first described, indicating that improving the uniformity of electric field at the SiC/oxide interface is essential to improve the area efficiency. A buried termination structure, where implanted zones are buried under a thin field buffer layer is proposed to obtain a nearly rectangular field distribution at the SiC/oxide interface. The termination pattern is then directly scaled without any iterative design process to optimize the termination area, and the simulation results show that the field distribution can be mostly preserved. Optimization and limitations that are related to fabrication and design considerations are also addressed in the end.

The complex layout of double sided power modules of electric vehicles and the risk of damage initiation and propagation in different interconnection layers necessitate a full three-dimensional model capturing all the details related to joining layers, power dies, terminals, and substrates. However, reliability of power modules is often simulated using simple models including only one power semiconductor die and the surrounding mold compound. In this work, a full model of a double sided power module with eight SiC dies per switch and the associated silver sintered layers is created to perform a thermal-mechanical analysis, and estimate the damage and lifetime of silver layers. Each die and the spacer bonded to it includes three silver layers: the top silver layer between the spacer and the top ceramic substrate, the middle silver layer between the die and the spacer, and the bottom silver layer between the bottom ceramic layer and the spacer. In this study, we used Anand viscoplastic model to represent material behavior of sintered silver. The damage parameter used for lifetime prediction was accumulated equivalent inelastic strain. This detailed finite element model enables accurate calculation of damage distribution in different silver layers, and study of the effect of the manufacturing parameters such as heatsink mounting pressure, as well as the effect of the neighboring joints and terminals on lifetime and reliability.

Graphene layers have a very high basal plane thermal conductivity, but a low conductivity out-of-plane. When placed on a heat source, they can efficiently spread heat laterally, but not vertically. To fully exploit ultrahigh basal plane thermal conductivity of graphene layers, they can be assembled vertically. We examine the efficiency of vertically aligned graphene layers as thermal interface material (TIM) for gallium nitride (GaN) high electrons mobility transistors (HEMTs) with ceramic packages. The junction temperature (Tj) is directly measured using thermocouples bonded to the die. The measurements are done under free convection in the ambient. The graphene results are compared with two conventional TIMs. It is shown the graphene TIM can lower the Tj by at least 5 °C. More temperature reduction is expected when testing with forced cooling. A transient thermal finite element model is also used for temperature prediction, showing good agreement with the experimental data.

The 3.3 kV SiC MOSFETs are essential for traction applications, so it is important to investigate the reliability of the recently developed high voltage MOSFETs and power modules as they are believed to be more susceptible to the effects of basal plane dislocations (BPDs). This paper presents measurement results and analysis of bipolar degradation and threshold voltage instability in 3.3 kV SiC MOSFETs having two distinct kinds of integrated diode, conventional body diode and embedded Schottky Barrier Diode (SBD). No bipolar degradation was observed both in MOSFET with conventional body diode and with embedded SBD after accumulated test with 100 hours each of 200%, 400% and 600% rated current stress in the 3rd quadrant of operation. However, the output characteristics show 1% ( 0.2 mΩ) and 2% ( 0.4 mΩ) increase in on resistance (RDS(on)) and 11% (0.23 V) and 5% (0.1 V) increase in threshold voltage (VTH), respectively, after total bipolar degradation test in the case of the MOSFET with conventional body diode and up to 74 hrs of 600% rated current stress in the case of the MOSFET with embedded SBD at 70°C. A rapid large negative VTH shift was obse rved in the MOSFETs with embedded SBD after 74 hrs of 600% rated current stress. After accumulated Bias Temperature Instability (BTI) test at 150°C, the VTH value at 25°C has increased by 9.7% (0.14 V) and 14.5% (0.2 V) for the MOSFET with conventional body diode and with embedded SBD, respectively, while RDS(on) increased by 1mΩ at 25°C and by 5mΩ at 150°C, for both types of MOSFETs.

Double sided modules accommodating wide band gap (WBG) devices are increasingly used in electric vehicles owing to their lower thermal resistance and parasitic inductances. Compared with single sided modules having a single ceramic substrate, the mechanical constraint applied on the silver sintered bonding layers in double sided modules (with two ceramic substrates) poses a more challenging reliability issue. In this work, we develop a parametric model to investigate the effects of layout, geometry and material properties on damage distribution in silver sintered layers of double sided modules. Anand viscoplastic model was used to describe the inelastic deformation of sintered silver under power cycling. Equivalent inelastic strain accumulated in each power cycle was used as the damage parameter and failure criterion. The model enables parametric study of damage distribution in double sided modules, and help improve design for maximum reliability. Using this model, the effects of parameters such as spacer and die thicknesses were investigated in this study.

In this work, MeV alpha particles generated from an accelerator are used to study single event breakdown (SEB) in 4H-SiC MOSFET samples, rated at 3.3 kV. The samples are exposed to bursts of alpha particles under reverse bias conditions to investigate the SEB sensitivity to ion energy and reverse bias. The energies of alpha particles are chosen to reach different depths in the drift region of the MOSFET devices, and also to penetrate the whole drift region. Forward and reverse characteristics are measured after each exposure, as long as no failures occur, to ensure that the device performance is maintained. The measurements show that no significant effects are observed on the drain-source leakage current, while minor effects on gate behavior can be seen as a function of accumulated fluence. Furthermore, SEB can only be triggered with a reverse bias larger than, or equal to 3 kV. A standard MOSFET cell with a similar rated voltage is also simulated in Sentaurus TCAD to study these effects, using two different models for the incident ion-induced ionization: the Alpha Particle and the Heavy Ion model. Simulations show that the Alpha Particle model cannot induce any device failures even with a 3.5 kV reverse bias, while it is possible to trigger a failure by the Heavy Ion model, where the ionization can be selected. Carrier plasma and internal electric field distributions of the two models are plotted and compared, showing that device failures triggered by a heavy ion are related to the hole injection at epi-substrate interface, in which linear energy transfer (LET) of the particle plays an important role.

SiC MOSFETs display reliability issues related to the quality of SiO2/SiC interface and bulk material due to the presence of near interface traps and point and extended material defects [1]. These material related issues give rise to a degradation of device reliability and ruggedness. One of them are basal plane dislocations (BPDs) introduced in the drift-layer during the epitaxial growth process which causes a s.c. bipolar degradation. Growth and movement of BPDs fueled by recombination energy has a very significant impact on conduction loss and on-resistance degradation. For 3.3 kV voltage capability, the probability of the appearance of BPDs is greater because the drift region is about three times larger compared to 1.2 kV devices [2-3]. We present measurement results and analysis of bipolar degradation in 3.3 kV MOSFETs with conventional body diode and embedded schottky barrier diode (SBD). The measurements were performed applying 50 % and 80 % of rated current with duty cycle 80 %, under total time of 100 hrs at constant case temperature of 54 °C. The 3rd-quadrant performance of both types of MOSFETs in pre-stress conditions was characterized at 25 and 150 °C with different gate biases of -10 V, 0 V, and +17 V. To evaluate the bipolar degradation, the diode conduction characteristics were measured at 25 °C after different stressing times by diode conduction the MOSFET output characteristics were measured at 25 and 54 °C before and after stressing the intrinsic body diode and embedded SBD. No VSD shift was observed in diode conduction characteristics. The results indicate that the MOSFETs were fabricated on appropriate material with a sufficiently low number basal plane dislocation (BPD). The on-state resistance with VGS = +17 V was decreased by temperature due to increased JFET resistance rather than bipolar degradation. On the other hand, the on-state resistance with VGS = +11 V was impacted by the increased temperature and VTH instability.

In this paper, Shockley-Read-Hall (SRH) lifetime depth profiles in the drift layer of 10 kV SiC PiN diodes are calculated after MeV proton implantation. It is assumed that the carbon vacancy will be the domination trap for charge carrier recombination and the SRH lifetime is calculated with defect parameters from the literature and proton-induced defect distributions deduced from SRIM calculations. The lifetime profiles are imported to Sentaurus TCAD and static and dynamic simulations using tailored lifetime profiles are carried out to study the electrical effect of proton implantation parameters. The results are compared to measurements, specializing on optimization of the trade off between on-state and turn-off losses, represented by the forward voltage drop, VT, and reverse recovery charge, Qrr, respectively. Both the simulated and measured IV characteristics show that increasing proton dose, or energy, has the effect on increasing forward voltage drop and on-state losses, while simultaneously, the localized SRH lifetime drop decreases the plasma level, increases the speed of recombination and decreases reverse recovery charge. Finally, TCAD simulations with different combinations of proton energies and fluences are used to optimize the trade-off between static and dynamic performances. Reverse recovery charge and forward voltage drops of these groups of diodes are plotted together, showing that a medium energy which induces the most defects in the depletion region relatively close to the anode gives the best dynamic performances, with a minimum cost of static performance.