The paper presents a comparative analysis between a single side cooled (SSC) power module (PM) and two double side cooled (DSC) PMs - a flip-chip and a non-flip-chip arrangements. These three PM layouts are compared in terms of footprint size, parasitic capacitance, stray inductance, thermal impedance, switching performance, and power loss under the same conditions. The results indicate that the SSC PM has the lowest parasitic capacitance and inductance, whereas the flip-chip DSC PM has the highest power density (smallest footprint), and despite that it has the lowest thermal impedance. Overall, the non-flip-chip DSC PM has the least favorable characteristics among the three layouts.

High-density electronics packaging requires fabrication of intricate conductive and dielectric features within a dense three-dimensional structure. Simultaneous deposition of both conductive and insulative printing materials using multimaterial additive manufacturing (AM) provides new opportunities to fabricate electronics packages with complex designs. This article reports the first demonstration of fully printed power die-embedded electronics package for wide band-gap devices. For this purpose, multimaterial inkjet AM was used to print a 0.5-mm thick electronics package for gallium nitride (GaN) power chips. The conductive parts of the package, including traces and vias, were printed using a high electrical conductivity silver ink, while a polyimide ink was used to print dielectric parts. The electrical characterization tests showed the reasonable performance of the printed package. While the conventional embedded packaging includes many steps such as laminating, plating, and drilling, which creates significant material waste and environmental issues, the proposed AM approach is done in a single step without material waste. 

The complex layout of double sided power modules of electric vehicles and the risk of damage initiation and propagation in different interconnection layers necessitate a full three-dimensional model capturing all the details related to joining layers, power dies, terminals, and substrates. However, reliability of power modules is often simulated using simple models including only one power semiconductor die and the surrounding mold compound. In this work, a full model of a double sided power module with eight SiC dies per switch and the associated silver sintered layers is created to perform a thermal-mechanical analysis, and estimate the damage and lifetime of silver layers. Each die and the spacer bonded to it includes three silver layers: the top silver layer between the spacer and the top ceramic substrate, the middle silver layer between the die and the spacer, and the bottom silver layer between the bottom ceramic layer and the spacer. In this study, we used Anand viscoplastic model to represent material behavior of sintered silver. The damage parameter used for lifetime prediction was accumulated equivalent inelastic strain. This detailed finite element model enables accurate calculation of damage distribution in different silver layers, and study of the effect of the manufacturing parameters such as heatsink mounting pressure, as well as the effect of the neighboring joints and terminals on lifetime and reliability.

Graphene layers have a very high basal plane thermal conductivity, but a low conductivity out-of-plane. When placed on a heat source, they can efficiently spread heat laterally, but not vertically. To fully exploit ultrahigh basal plane thermal conductivity of graphene layers, they can be assembled vertically. We examine the efficiency of vertically aligned graphene layers as thermal interface material (TIM) for gallium nitride (GaN) high electrons mobility transistors (HEMTs) with ceramic packages. The junction temperature (Tj) is directly measured using thermocouples bonded to the die. The measurements are done under free convection in the ambient. The graphene results are compared with two conventional TIMs. It is shown the graphene TIM can lower the Tj by at least 5 °C. More temperature reduction is expected when testing with forced cooling. A transient thermal finite element model is also used for temperature prediction, showing good agreement with the experimental data.

Double sided modules accommodating wide band gap (WBG) devices are increasingly used in electric vehicles owing to their lower thermal resistance and parasitic inductances. Compared with single sided modules having a single ceramic substrate, the mechanical constraint applied on the silver sintered bonding layers in double sided modules (with two ceramic substrates) poses a more challenging reliability issue. In this work, we develop a parametric model to investigate the effects of layout, geometry and material properties on damage distribution in silver sintered layers of double sided modules. Anand viscoplastic model was used to describe the inelastic deformation of sintered silver under power cycling. Equivalent inelastic strain accumulated in each power cycle was used as the damage parameter and failure criterion. The model enables parametric study of damage distribution in double sided modules, and help improve design for maximum reliability. Using this model, the effects of parameters such as spacer and die thicknesses were investigated in this study.

Residual stresses created during the packaging process can adversely affect the reliability of electronics components. We used incremental hole-drilling method, following the ASTM E 837-20 standard, to measure packaging induced residual stresses in discrete packages of power electronics components. For this purpose, we bonded a strain gauge on the surface of a Gallium Nitride (GaN) power component, drilled a hole through the thickness of the component in several incremental steps, recorded the relaxed strain data on the sample surface using the strain gauge, and finally calculated the residual stresses from the measured strain data. The recorded strains and the residual stresses are related by the compliance coefficients. For the hole drilling method in the isotropic materials, the compliance coefficients are calculated from the analytical solutions, and available in the ASTM standard. But for the orthotropic multilayered components typically found in microelectronics assemblies, numerical solutions are necessary. We developed a subroutine in ANSYS APDL to calculate the compliance coefficients of the hole drilling test in the molded and embedded power electronics components. This can extend the capability of the hole drilling method to determine residual stresses in more complex layered structures found in electronics. 

Compared with silicon-based power devices, wide band gap (WBG) semiconductor devices operate at significantly higher power densities required in applications such as electric vehicles and more electric airplanes. This necessitates development of power electronics packages with enhanced thermal characteristics that fulfil the electrical insulation requirements. The present research investigates the feasibility of using ceramic additive manufacturing (AM), also known as three-dimensional (3D) printing, to address thermal and electrical requirements in packaging gallium nitride (GaN) based high-electron-mobility transistors (HEMTs). The goal is to exploit design freedom and manufacturing flexibility provided by ceramic AM to fabricate power device packages with a lower junction-to-ambient thermal resistance (<italic>R</italic>&#x03B8;JA). Ceramic AM also enables incorporation of intricate 3D features into the package structure in order to control the isolation distance between the package source and drain contact pads. Moreover, AM allows to fabricate different parts of the packaging assembly as a single structure to avoid high thermal resistance interfaces. For example, the ceramic package and the ceramic heatsink can be printed as a single part without any bonding layer. Thermal simulations under different thermal loading and cooling conditions show the improvement of thermal performance of the package fabricated by ceramic AM. If assisted by an efficient cooling strategy, the proposed package has the potential to reduce <italic>R</italic>&#x03B8;JA by up to 48%. The results of the preliminary efforts to fabricate the ceramic package by AM are presented, and the challenges that have to be overcome for further development of this manufacturing method are recognized and discussed. 

Additive manufacturing (AM) of large-scale polymer and composite parts using robotic arms integrated with extruders has received significant attention in recent years. Despite the contributions of great technical progress and material development towards optimizing this manufacturing method, different failure modes observed in the final printed products have hindered its application in producing large engineering structures used in aerospace and automotive industries. We report failure modes in a variety of printed polymer and composite parts, including fuel tanks and car bumpers. Delamination and warpage observed in these parts originate mostly from thermal gradients and residual stresses accumulated during material deposition and cooling. Because printing large structures requires expensive resources, process simulation to recognize the possible failure modes can significantly lower the manufacturing cost. In this regard, accurate prediction of temperature distribution using thermal simulations is the first step. Finite element analysis (FEA) was used for process simulation of large-scale robotic AM. The important steps of the simulation are presented, and the challenges related to the modeling are recognized and discussed in detail. The numerical results showed reasonable agreement with the temperature data measured by an infrared camera. While in small-scale extrusion AM, the cooling time to the glassy state is less than 1 s, in large-scale AM, the cooling time is around two orders of magnitudes longer. © 2022 by the authors

Silicon carbide (SiC) power devices are steadily increasing their market share in various power electronics applications. However, they require low-inductive packaging in order to realize their full potential. In this research, low-inductive layouts for half-bridge power modules, using a direct bonded copper (DBC) substrate, that are suitable for SiC power devices, were designed and tested. To reduce the negative effects of the switching transients on the gate voltage, flexible printed circuit boards (PCBs) were used to interconnect the gate and source pins of the module with the corresponding pads of the power chips. In addition, conductive springs were used as low inductive, solder-free contacts for the module power terminals. The module casing and lid were produced using additive manufacturing, also known as 3D printing, to create a compact design. It is shown that the inductance of this module is significantly lower than the commercially available modules.