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  • 1.
    Carlsson, Mats
    et al.
    RISE., Swedish ICT, SICS, Computer Systems Laboratory.
    Schulte, Christian
    RISE., Swedish ICT, SICS.
    Finite domain constraint programming systems2002Annet (Annet vitenskapelig)
  • 2.
    Castaneda Lozano, Roberto
    et al.
    RISE - Research Institutes of Sweden, ICT, SICS. KTH Royal Institute of Technology, Sweden .
    Carlsson, Mats
    RISE - Research Institutes of Sweden, ICT, SICS.
    Blindell, Gabriel
    KTH Royal Institute of Technology, Sweden .
    Schulte, Christian
    RISE - Research Institutes of Sweden, ICT, SICS. KTH Royal Institute of Technology, Sweden .
    Combinatorial register allocation and instruction scheduling2019Inngår i: ACM Transactions on Programming Languages and Systems, ISSN 0164-0925, E-ISSN 1558-4593, Vol. 41, nr 3, artikkel-id 17Artikkel i tidsskrift (Fagfellevurdert)
    Abstract [en]

    This article introduces a combinatorial optimization approach to register allocation and instruction scheduling, two central compiler problems. Combinatorial optimization has the potential to solve these problems optimally and to exploit processor-specific features readily. Our approach is the first to leverage this potential in practice: it captures the complete set of program transformations used in state-of-the-art compilers, scales to medium-sized functions of up to 1,000 instructions, and generates executable code. This level of practicality is reached by using constraint programming, a particularly suitable combinatorial optimization technique. Unison, the implementation of our approach, is open source, used in industry, and integrated with the LLVM toolchain. An extensive evaluation confirms that Unison generates better code than LLVM while scaling to medium-sized functions. The evaluation uses systematically selected benchmarks from MediaBench and SPEC CPU2006 and different processor architectures (Hexagon, ARM, MIPS). Mean estimated speedup ranges from 1.1% to 10% and mean code size reduction ranges from 1.3% to 3.8% for the different architectures. A significant part of this improvement is due to the integrated nature of the approach. Executing the generated code on Hexagon confirms that the estimated speedup results in actual speedup. Given a fixed time limit, Unison solves optimally functions of up to 946 instructions, nearly an order of magnitude larger than previous approaches. The results show that our combinatorial approach can be applied in practice to trade compilation time for code quality beyond the usual compiler optimization levels, identify improvement opportunities in heuristic algorithms, and fully exploit processor-specific features.

  • 3.
    Castaneda Lozano, Roberto
    et al.
    RISE., Swedish ICT, SICS, Computer Systems Laboratory.
    Carlsson, Mats
    RISE., Swedish ICT, SICS, Computer Systems Laboratory.
    Drejhammar, Frej
    RISE., Swedish ICT, SICS, Computer Systems Laboratory.
    Schulte, Christian
    RISE., Swedish ICT, SICS, Computer Systems Laboratory.
    Constraint-based Register Allocation and Instruction Scheduling2012Konferansepaper (Fagfellevurdert)
    Abstract [en]

    This paper introduces a constraint model and solving techniques for code generation in a compiler back-end. It contributes a new model for global register allocation that combines several advanced aspects: multiple register banks (subsuming spilling to memory), coalescing, and packing. The model is extended to include instruction scheduling and bundling. The paper introduces a decomposition scheme exploiting the underlying program structure and exhibiting robust behavior for functions with thousands of instructions. Evaluation shows that code quality is on par with LLVM, a state-of-the-art compiler infrastructure. The paper makes important contributions to the applicability of constraint programming as well as compiler construction: essential concepts are unified in a high-level model that can be solved by readily available modern solvers. This is a significant step towards basing code generation entirely on a high-level model and by this facilitates the construction of correct, simple, flexible, robust, and high-quality code generators.

  • 4.
    Castaneda Lozano, Roberto
    et al.
    RISE., Swedish ICT, SICS, Computer Systems Laboratory.
    Carlsson, Mats
    RISE., Swedish ICT, SICS, Computer Systems Laboratory.
    Hjort Blindell, Gabriel
    KTH Royal Institute of Technology, Sweden.
    Schulte, Christian
    RISE., Swedish ICT, SICS, Computer Systems Laboratory.
    Combinatorial Spill Code Optimization and Ultimate Coalescing2014Konferansepaper (Fagfellevurdert)
    Abstract [en]

    This paper presents a novel combinatorial model that integrates global register allocation based on ultimate coalescing, spill code optimization, register packing, and multiple register banks with instruction scheduling (including VLIW). The model exploits alternative temporaries that hold the same value as a new concept for ultimate coalescing and spill code optimization. The paper presents Unison as a code generator based on the model and advanced solving techniques using constraint programming. Thorough experiments using MediaBench and a processor (Hexagon) that are typical for embedded systems demonstrate that Unison: is robust and scalable; generates faster code than LLVM (up to 41% with a mean improvement of 7%); possibly generates optimal code (for 29% of the experiments); effortlessly supports different optimization criteria (code size on par with LLVM). Unison is significant as it addresses the same aspects as traditional code generation algorithms, yet is based on a simple integrated model and robustly can generate optimal code.

  • 5.
    Castaneda Lozano, Roberto
    et al.
    RISE., Swedish ICT, SICS, Computer Systems Laboratory. KTH Royal Institute of Technology, Sweden.
    Carlsson, Mats
    RISE., Swedish ICT, SICS, Computer Systems Laboratory.
    Hjort Blindell, Gabriel
    KTH Royal Institute of Technology, Sweden.
    Schulte, Christian
    RISE., Swedish ICT, SICS, Computer Systems Laboratory. KTH Royal Institute of Technology, Sweden.
    Register allocation and instruction scheduling in Unison2016Inngår i: Proceedings of the 25th International Conference on Compiler Construction, 2016, 6, s. 263-264Konferansepaper (Fagfellevurdert)
    Abstract [en]

    This paper describes Unison, a simple, flexible, and potentially optimal software tool that performs register allocation and instruction scheduling in integration using combinatorial optimization. The tool can be used as an alternative or as a complement to traditional approaches, which are fast but complex and suboptimal. Unison is most suitable whenever high-quality code is required and longer compilation times can be tolerated (such as in embedded systems or library releases), or the targeted processors are so irregular that traditional compilers fail to generate satisfactory code.

  • 6.
    Castaneda Lozano, Roberto
    et al.
    RISE., Swedish ICT, SICS, Computer Systems Laboratory.
    Hjort Blindell, Gabriel
    Carlsson, Mats
    RISE., Swedish ICT, SICS, Computer Systems Laboratory.
    Drejhammar, Frej
    RISE., Swedish ICT, SICS, Computer Systems Laboratory.
    Schulte, Christian
    RISE., Swedish ICT, SICS, Computer Systems Laboratory.
    Constraint-based Code Generation2013Konferansepaper (Fagfellevurdert)
  • 7.
    Castaneda Lozano, Roberto
    et al.
    RISE., Swedish ICT, SICS, Computer Systems Laboratory.
    Schulte, Christian
    RISE., Swedish ICT, SICS, Computer Systems Laboratory.
    Survey on Combinatorial Register Allocation and Instruction Scheduling2014Inngår i: arXiv:1409.7628 [cs.PL]Artikkel i tidsskrift (Fagfellevurdert)
    Abstract [en]

    Register allocation and instruction scheduling are two central compiler back-end problems that are critical for quality. In the last two decades, combinatorial optimization has emerged as an alternative approach to traditional, heuristic algorithms for these problems. Combinatorial approaches are generally slower but more flexible than their heuristic counterparts and have the potential to generate optimal code. This paper surveys existing literature on combinatorial register allocation and instruction scheduling. The survey covers approaches that solve each problem in isolation as well as approaches that integrate both problems. The latter have the potential to generate code that is globally optimal by capturing the trade-off between conflicting register allocation and instruction scheduling decisions.

  • 8.
    Castaneda Lozano, Roberto
    et al.
    RISE., Swedish ICT, SICS, Computer Systems Laboratory.
    Schulte, Christian
    RISE., Swedish ICT, SICS, Computer Systems Laboratory.
    Wahlberg, Lars
    Testing Continuous Double Auctions with a Constraint-based Oracle2010Konferansepaper (Fagfellevurdert)
    Abstract [en]

    Computer trading systems are essential for today's financial markets where the trading systems' correctness is of paramount economical significance. Automated random testing is a useful technique to find bugs in these systems, but it requires an independent system to decide the correctness of the system under test (known as oracle problem). This paper introduces a constraint-based oracle for random testing of a real-world trading system. The oracle provides the expected results by generating and solving constraint models of the trading system's continuous double auction. Constraint programming is essential for the correctness of the test oracle as the logic for calculating trades can be mapped directly to constraint models. The paper shows that the generated constraint models can be solved efficiently. Most importantly, the approach is shown to be successful by finding errors in a deployed financial trading system and in its specification.

  • 9.
    Castañedalozano, Roberto
    et al.
    KTH Royal Institute of Technology, Sweden.
    Schulte, Christian
    RISE - Research Institutes of Sweden, ICT, SICS.
    Survey on combinatorial register allocation and instruction scheduling2019Inngår i: ACM Computing Surveys, ISSN 0360-0300, E-ISSN 1557-7341, Vol. 52, nr 3, artikkel-id 62Artikkel i tidsskrift (Fagfellevurdert)
    Abstract [en]

    Register allocation (mapping variables to processor registers or memory) and instruction scheduling (reordering instructions to increase instruction-level parallelism) are essential tasks for generating efficient assembly code in a compiler. In the past three decades, combinatorial optimization has emerged as an alternative to traditional, heuristic algorithms for these two tasks. Combinatorial optimization approaches can deliver optimal solutions according to a model, can precisely capture trade-offs between conflicting decisions, and are more flexible at the expense of increased compilation time. This article provides an exhaustive literature review and a classification of combinatorial optimization approaches to register allocation and instruction scheduling, with a focus on the techniques that are most applied in this context: integer programming, constraint programming, partitioned Boolean quadratic programming, and enumeration. Researchers in compilers and combinatorial optimization can benefit from identifying developments, trends, and challenges in the area; compiler practitioners may discern opportunities and grasp the potential benefit of applying combinatorial optimization. .

  • 10.
    Corcoran, Diarmuid
    et al.
    Ericsson AB, Sweden.
    Andimeh, Loghman
    Ericsson AB, Sweden.
    Ermedahl, Andreas
    Ericsson AB, Sweden.
    Kreuger, Per
    RISE - Research Institutes of Sweden, ICT, SICS.
    Schulte, Christian
    KTH Royal Institute of Technology, Sweden.
    Data driven selection of DRX for energy efficient 5G RAN2017Konferansepaper (Fagfellevurdert)
    Abstract [en]

    The number of connected mobile devices is increasing rapidly with more than 10 billion expected by 2022. Their total aggregate energy consumption poses a significant concern to society. The current 3gpp (3rd Generation Partnership Project) LTE/LTE-Advanced standard incorporates an energy saving technique called discontinuous reception (DRX). It is expected that 5G will use an evolved variant of this scheme. In general, the single selection of DRX parameters per device is non trivial. This paper describes how to improve energy efficiency of mobile devices by selecting DRX based on the traffic profile per device. Our particular approach uses a two phase data-driven strategy which tunes the selection of DRX parameters based on a smart fast energy model. The first phase involves the off-line selection of viable DRX combinations for a particular traffic mix. The second phase involves an on-line selection of DRX from this viable list. The method attempts to guarantee that latency is not worse than a chosen threshold. Alternatively, longer battery life for a device can be traded against increased latency. We built a lab prototype of the system to verify that the technique works and scales on a real LTE system. We also designed a sophisticated traffic generator based on actual user data traces. Complementary method verification has been made by exhaustive off-line simulations on recorded LTE network data. Our approach shows significant device energy savings, which has the aggregated potential over billions of devices to make a real contribution to green, energy efficient networks.

  • 11.
    Drejhammar, Frej
    et al.
    RISE., Swedish ICT, SICS, Computer Systems Laboratory.
    Haridi, Seif
    RISE., Swedish ICT, SICS, Computer Systems Laboratory.
    Brand, Per
    RISE., Swedish ICT, SICS, Computer Systems Laboratory.
    Schulte, Christian
    Flow Java: declarative concurrency for Java.2003Inngår i: Proceedings of the Nineteenth International Conference on Logic Programming, 2003, 1Konferansepaper (Fagfellevurdert)
    Abstract [en]

    Logic variables pioneered by (concurrent) logic and concurrent constraint programming are powerful mechanisms for automatically synchronizing concurrent computations. They support a declarative model of concurrency that avoids explicitly suspending and resuming computations. This paper presents Flow Java which conservatively extends Java with single assignment variables and futures as variants of logic variables. The extension is conservative with respect to object-orientation, types, parameter passing, and concurrency in Java. Futures support secure concurrent abstractions and are essential for seamless integration of single assignment variables into Java. We show how Flow Java supports the construction of simple and concise concurrent programming abstractions. We present how to moderately extend compilation and the runtime architecture of an existing Java implementation for Flow Java. Evaluation using standard Java benchmarks shows that in most cases the overhead is between 10% and 40%. For some pathological cases the runtime increases by up to 75%.

  • 12.
    Drejhammar, Frej
    et al.
    RISE., Swedish ICT, SICS, Computer Systems Laboratory.
    Schulte, Christian
    Implementation strategies for single assignment variables2004Konferansepaper (Fagfellevurdert)
  • 13.
    Haridi, Seif
    et al.
    RISE - Research Institutes of Sweden, ICT, SICS.
    van Roy, Peter
    Brand, Per
    RISE - Research Institutes of Sweden, ICT, SICS.
    Schulte, Christian
    Programming languages for distributed applications1998Inngår i: New generation computing, ISSN 0288-3635, E-ISSN 1882-7055, Vol. 16, nr 3, s. 223-261Artikkel i tidsskrift (Fagfellevurdert)
  • 14.
    Hjort Blindell, Gabriel
    et al.
    RISE - Research Institutes of Sweden, ICT, SICS. KTH Royal Institute of Technology, Sweden.
    Carlsson, Mats
    RISE - Research Institutes of Sweden, ICT, SICS.
    Lozano, Roberto C.
    RISE - Research Institutes of Sweden, ICT, SICS. KTH Royal Institute of Technology, Sweden.
    Schulte, Christian
    RISE - Research Institutes of Sweden, ICT, SICS. KTH Royal Institute of Technology, Sweden.
    Complete and practical universal instruction selection2017Inngår i: ACM Transactions on Embedded Computing Systems, ISSN 1539-9087, E-ISSN 1558-3465, Vol. 16, nr 5s, artikkel-id 119Artikkel i tidsskrift (Fagfellevurdert)
    Abstract [en]

    In code generation, instruction selection chooses processor instructions to implement a program under compilation where code quality crucially depends on the choice of instructions. Using methods from combinatorial optimization, this paper proposes an expressive model that integrates global instruction selection with global code motion. The model introduces (1) handling of memory computations and function calls, (2) a method for inserting additional jump instructions where necessary, (3) a dependency-based technique to ensure correct combinations of instructions, (4) value reuse to improve code quality, and (5) an objective function that reduces compilation time and increases scalability by exploiting bounding techniques. The approach is demonstrated to be complete and practical, competitive with LLVM, and potentially optimal (w.r.t. the model) for medium-sized functions. The results show that combinatorial optimization for instruction selection is well-suited to exploit the potential of modern processors in embedded systems.

  • 15.
    Hjort Blindell, Gabriel
    et al.
    KTH Royal Institute of Technology, Sweden.
    Castaneda Lozano, Roberto
    RISE., Swedish ICT, SICS, Computer Systems Laboratory. KTH Royal Institute of Technology, Sweden.
    Carlsson, Mats
    RISE., Swedish ICT, SICS, Computer Systems Laboratory.
    Schulte, Christian
    RISE., Swedish ICT, SICS, Computer Systems Laboratory. KTH Royal Institute of Technology, Sweden.
    Modeling Universal Instruction Selection2015Inngår i: Principles and Practice of Constraint Programming, 2015, 7, Vol. 9255, s. 609-626Konferansepaper (Fagfellevurdert)
    Abstract [en]

    Instruction selection implements a program under compilation by selecting processor instructions and has tremendous impact on the performance of the code generated by a compiler. This paper introduces a graph-based universal representation that unifiees data and control flow for both programs and processor instructions. The representation is the essential prerequisite for a constraint model for instruction selection introduced in this paper. The model is demonstrated to be expressive in that it supports many processor features that are out of reach of state-of-the-art approaches, such as advanced branching instructions, multiple register banks, and SIMD instructions. The resulting model can be solved for small to medium size input programs and sophisticated processor instructions and is competitive with LLVM in code quality. Model and representation are significant due to their expressiveness and their potential to be combined with models for other code generation tasks.

  • 16. Schulte, Christian
    et al.
    Carlsson, Mats
    RISE., Swedish ICT, SICS, Computer Systems Laboratory.
    Finite domain constraint programming systems2006Inngår i: Handbook of constraint programming, Elsevier , 2006, 1Kapittel i bok, del av antologi (Fagfellevurdert)
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