Lead-free tin-based solder joints often have a single-grained structure with random orientation and highly anisotropic properties. These alloys are typically stiffer than lead-based solders, hence transfer more stress to printed circuit boards (PCBs) during thermal cycling. This may lead to cracking of the PCB laminate close to the solder joints, which could increase the PCB flexibility, alleviate strain on the solder joints, and thereby enhance the solder fatigue life. If this happens during accelerated thermal cycling it may result in overestimating the lifetime of solder joints in field conditions. In this study, the grain structure of SAC305 solder joints connecting ceramic resistors to PCBs was studied using polarized light microscopy and was found to be mostly single-grained. After thermal cycling, cracks were observed in the PCB under the solder joints. These cracks were likely formed at the early stages of thermal cycling prior to damage initiation in the solder. A finite element model incorporating temperature-dependant anisotropic thermal and mechanical properties of single-grained solder joints is developed to study these observations in detail. The model is able to predict the location of damage initiation in the PCB and the solder joints of ceramic resistors with reasonable accuracy. It also shows that the PCB cracks of even very small lengths may significantly reduce accumulated creep strain and creep work in the solder joints. The proposed model is also able to evaluate the influence of solder anisotropy on damage evolution in the neighbouring (opposite) solder joints of a ceramic resistor.

Residual stresses created during the packaging process can adversely affect the reliability of electronics components. We used incremental hole-drilling method, following the ASTM E 837-20 standard, to measure packaging induced residual stresses in discrete packages of power electronics components. For this purpose, we bonded a strain gauge on the surface of a Gallium Nitride (GaN) power component, drilled a hole through the thickness of the component in several incremental steps, recorded the relaxed strain data on the sample surface using the strain gauge, and finally calculated the residual stresses from the measured strain data. The recorded strains and the residual stresses are related by the compliance coefficients. For the hole drilling method in the isotropic materials, the compliance coefficients are calculated from the analytical solutions, and available in the ASTM standard. But for the orthotropic multilayered components typically found in microelectronics assemblies, numerical solutions are necessary. We developed a subroutine in ANSYS APDL to calculate the compliance coefficients of the hole drilling test in the molded and embedded power electronics components. This can extend the capability of the hole drilling method to determine residual stresses in more complex layered structures found in electronics. 

Compared with silicon-based power devices, wide band gap (WBG) semiconductor devices operate at significantly higher power densities required in applications such as electric vehicles and more electric airplanes. This necessitates development of power electronics packages with enhanced thermal characteristics that fulfil the electrical insulation requirements. The present research investigates the feasibility of using ceramic additive manufacturing (AM), also known as three-dimensional (3D) printing, to address thermal and electrical requirements in packaging gallium nitride (GaN) based high-electron-mobility transistors (HEMTs). The goal is to exploit design freedom and manufacturing flexibility provided by ceramic AM to fabricate power device packages with a lower junction-to-ambient thermal resistance (<italic>R</italic>&#x03B8;JA). Ceramic AM also enables incorporation of intricate 3D features into the package structure in order to control the isolation distance between the package source and drain contact pads. Moreover, AM allows to fabricate different parts of the packaging assembly as a single structure to avoid high thermal resistance interfaces. For example, the ceramic package and the ceramic heatsink can be printed as a single part without any bonding layer. Thermal simulations under different thermal loading and cooling conditions show the improvement of thermal performance of the package fabricated by ceramic AM. If assisted by an efficient cooling strategy, the proposed package has the potential to reduce <italic>R</italic>&#x03B8;JA by up to 48%. The results of the preliminary efforts to fabricate the ceramic package by AM are presented, and the challenges that have to be overcome for further development of this manufacturing method are recognized and discussed. 

Silicon carbide (SiC) power devices are steadily increasing their market share in various power electronics applications. However, they require low-inductive packaging in order to realize their full potential. In this research, low-inductive layouts for half-bridge power modules, using a direct bonded copper (DBC) substrate, that are suitable for SiC power devices, were designed and tested. To reduce the negative effects of the switching transients on the gate voltage, flexible printed circuit boards (PCBs) were used to interconnect the gate and source pins of the module with the corresponding pads of the power chips. In addition, conductive springs were used as low inductive, solder-free contacts for the module power terminals. The module casing and lid were produced using additive manufacturing, also known as 3D printing, to create a compact design. It is shown that the inductance of this module is significantly lower than the commercially available modules.

COSIVU is a three year collaborative research project that ended in September 2015 and which has been funded within the European Green Car Initiative (now the European Green Vehicle Initiative). COSIVU addresses one of the most critical technical parts in fully electrical vehicles (FEV) besides the energy storage system: the mechatronic drive-train unit. The COSIVU project has delivered a new system architecture for multiple wheel drive-trains by a smart, compact and durable single-wheel drive unit with integrated electric motor, full silicon carbide (SiC) power electronics (switches and diodes), a novel control and health monitoring module with wireless communication, and an advanced ultra-compact cooling solution. DfR utilizing FEM simulations ensures first time right solutions. This paper presents the main results including the architecture of the drive train solution as well as the modular design of the inverter based on Inverter Building Blocks, one per phase. Performance tests are presented here for the first time for both the heavy duty commercial vehicle solution performed in a test rig by Volvo, and the tests of the COSIVU solution adapted to a passenger car done by Elaphe.

The three year EU project SMARTER-SI that ends in January 2018 has tested a new concept for small lot manufacturing for SMEs which we call the Cooperative Foundry Model (CFM). During previous research, all RTOs have completed building blocks, i.e. components or parts of systems which are readily available and characterized by their high Technology Readiness Level (TRL). These building blocks are combined and integrated in so-called Application Experiments (AEs), thereby creating innovative Smart Systems that serve the SMEs' needs. Four pre defined AEs have been presented before [1] and in this paper, six additional AEs will be presented: i) a smart sensor for pneumatic combined clutch and brakes, ii) smart well plates for tissue engineering integrating continuous, non-invasive TEER iii) microclimate sensor for moisture applications, iv) LTCC-Si-Pressure Sensor, v) miniaturized capillary electrophoresis system for bio analysis, and vi) a MEMS sensor module for respiratory applications. Finally, a brief description of ongoing standardization efforts is presented.

The three year EU project SMARTER-SI that started in February 2015 has developed and tested a new production platform for smart systems that offer SMEs and “mid-cap” companies help to manufacture small and medium volumes. The ultimate goal of this project is to test a new concept for small lot production, which we call the Cooperative Foundry Model (CFM). The CFM is tested by combining components or parts of systems (building blocks) already developed by the RTOs involved in the project in so-called Application Experiments (AEs), thereby creating innovative Smart Systems which serve SMEs' product needs. During the first two years, four predefined AEs have been developed that consist of i) a multi-parametric point of care testing (POCT) device, ii) a dew-point measurement system, iii) a CO₂ measurement system, and iv) a portable device that can be used to screen water quality.

In order to place sensors or electronics in very high temperature environments, new materials and methods for interconnection are required. A comparative study between different electrical interconnection methods for very high operation temperatures (500 °C - 800 °C) is presented. Thermo-mechanical simulations and characterization of samples of the interconnection types during high temperature exposure are presented. The results of the thermo-mechanical simulations showed that stresses are low in a connection system based on liquid interconnection. This system, however, proved to be difficult to realize due to problems with oxides and sealing of the metallic liquid. Modeling of an interconnection based purely on mechanical pressure without any solder or metallic bond showed high stress. This was also confirmed during high temperature exposure where the connection failed. High stress was also predicted for an interconnection based on nano-Ag paste. The high temperature tests, however, showed promising results at 800 °C for over 100 hours. © 2011 IEEE.

Effectively removing dissipated heat from the switching devices enables a higher current carrying capability per chip area ratio, thus leading to smaller or fewer devices for a given power requirement specification. Further, the use of SiC based devices has proven to increase the efficiency of the system thereby reducing the dissipated heat. Thermal models have been used to compare SiC power modules. Single and double sided cooling have been simulated. The simulated maximum temperatures were 141 °C for the single sided version and 119.7 °C for the double sided version. In addition, the reliability of a single sided module and thermally induced plastic strains of a double sided module have been investigated. A local model of the wire bond interface to the transistor metallization shows a 3‰ maximum increase in plastic strain during the power cycle. Simulations of the creep strain rates in the die attach solder layer for a power cycling loads also shows a 3‰ increase in creep strain per cycle.

Silicon Carbide (SiC) based transistor devices have demonstrated higher efficiency switching operation compared to silicon-based, state-of-the-art solutions due to the superior electrical and thermal properties of the SiC material. The improved current density and thermal conductivity allows SiC-based power modules to be smaller than their silicon counterparts for comparable current densities. The active chip area can be reduced further by effectively cooling the devices. In this work, a new power module including SiC bipolar junction transistors (BJT) and diodes and integrated double sided cooling will be introduced. The target application of these modules is a new drive-train system for commercial electric vehicles.

The electrification of drive trains combined with special requirements of the automotive and heavy construction equipment applications drives the development of small, highly integrated and reliable power inverters. To minimize the volume and increase the reliability of the power switching devices a module consisting of SiC devices with double sided cooling capability has been developed. There are several benefits related to cooling the power devices on both sides. The major improvement is the ability to increase the power density, and thereby reduce the number of active switching devices required which in turn reduces costs. Other expected benefits of more efficient cooling are reductions in volume and mass per power ratio. Alternatively, improved reliability margins due to lower temperature swings during operation are can be expected. Removing the wire bonds on the top side of the devices is expected to improve the reliability regardless, since wire bonds are known to be one of the main limitations in power switching devices. In addition, it is possible to design the package with substantially lower inductance, which can allow faster switching of the devices. In this paper the design, simulations and fabrication process of a double sided SiC-based power module are presented.

Cooling power modules on both sides of the active switching devices reduces the operational junction temperature compared to conventional single sided cooling. In this work, thermal simulations of power modules based on single sided cooling concepts are compared with double sided cooling counterparts. Expected junction temperatures, maximum temperatures and maximum current capability is analyzed. In addition, experimental verification in the form of comparisons with thermal characterization tests for both single-And double sided power modules based on SiC bipolar junction transistors is presented. Results from simulations show that cooling of both sides of the active switching devices can reduce the thermal resistance by more than 40 percent. This number depends on the heat transfer coefficient. From one example, simulating a worst case stall condition of the electric machine, the use of double sided cooling reduces the maximum junction temperature from 167 °C to 106 °C at a load current of 300 A using a heat transfer coefficient of 4 kW/m2K and 4 kHz switching frequency. Furthermore, the temperature decreases to 97°C if AlN-based DBC substrates are used instead of alumina DBCs. Results from the experimental comparison between double-And single sided cooling showed that the maximum temperature for a load current range of 15 A to 50 A was reduced by 18 percent to 55 percent by using double sided cooling. At a device temperature of 60 °C, the increased thermal capability of the double sided version allowed for a 20 A higher load current, which corresponded to operation under 50 percent higher power losses. Double sided cooling also increased the maximum current capability through a single SiC BJT by more than 20 percent beyond the maximum current capability through the single sided cooling version.

As the automotive industry shifts towards the electrification of drive trains, the efficiency of power electronics becomes more important. The use of silicon carbide (SiC) devices in power electronics has shown several benefits in efficiency, blocking voltage and high temperature operation. In addition, the ability of SiC to operate at higher frequencies due to lower switching losses can result in reduced weight and volume of the system, which also are important factors in vehicles. However, the reliability of packaged SiC devices is not yet fully assessed. Previous work has predicted that the different material properties of SiC compared to Si could have a large influence on the failure mechanisms and reliability. For example, the much higher elastic modulus of SiC compared to Si could increase strain on neighboring materials during power cycling. In this work, the failure mechanisms of packaged Si- and SiC-based power devices have been investigated following power cycling tests. The packaged devices were actively cycled in 4.5 s heating and 20 s cooling at ΔT = 60 - 80 K. A failure analysis using micro-focus X-ray and scanning acoustic microscopy (SAM) was carried out in order to determine the most important failure mechanisms. The results of the analysis indicate that the dominant failure mechanism is wire bond liftoff at the device chip for all of the SiC-based devices. Further analysis is required to determine the exact failure mechanisms of the analyzed Si-based devices. In addition, the SiC-based devices failed before the Si-based devices, which could be a result of the different properties of the SiC material.

The increasing complexity of electronics in systems used in safety critical applications, such as for example self-driving vehicles requires new methods to assure the hardware reliability of the electronic assemblies. Prognostics and Health Management (PHM) that uses a combination of data-driven and Physics-of-Failure models is a promising approach to avoid unexpected failures in the field. However, to enable PHM based partly on Physics-of-Failure models, sensor data that measures the relevant environment loads to which the electronics is subjected during its mission life are required. In this work, the feasibility to manufacture and use integrated sensors in the inner layers of a printed circuit board (PCB) as mission load indicators measuring impacts and vibrations has been investigated. A four-layered PCB was designed in which piezoelectric sensors based on polyvinylidenefluoride-co-trifluoroethylene (PVDF-TrFE) were printed on one of the laminate layers before the lamination process. Manufacturing of the PCB was followed by the assembly of components consisting of BGAs and QFN packages in a standard production reflow soldering process. Tests to ensure that the functionality of the sensor material was unaffected by the soldering process were performed. Results showed a yield of approximately 30 % of the sensors after the reflow soldering process. The yield was also dependent on sensor placement and possibly shape. Optimization of the sensor design and placement is expected to bring the yield to 50 % or better. The sensors responded as expected to impact tests. Delamination areas were present in the test PCBs, which requires further investigation. The delamination does not seem to be due to the presence of embedded sensors alone but rather the result of a combination of several factors. The conclusion of this work is that it is feasible to embed piezoelectric sensors in the layers of a PCB.

The increasing complexity of electronics in systems used in safety critical applications, such as self-driving vehicles, requires new methods to assure the hardware reliability of the electronic assemblies. Prognostics and health management (PHM) that uses a combination of data-driven and physics-of-failure models is a promising approach to avoid unexpected failures in the field. However, to enable PHM based partly on physics-of-failure models, sensor data that measure the relevant environment loads to which the electronics are subjected during its mission life are required. In this work, the feasibility to manufacture and use integrated sensors in the inner layers of a printed circuit board (PCB) as mission load indicators measuring impacts and vibrations has been investigated. A four-layered PCB was designed in which piezoelectric sensors based on polyvinylidenefluoride-co-trifluoroethylene (PVDF-TrFE) were printed on one of the laminate layers before the lamination process. Manufacturing of the PCB was followed by the assembly of components consisting of ball grid arrays (BGAs) and quad flat no-leads (QFN) packages in a standard production reflow soldering process. Tests to ensure that the functionality of the sensor material was unaffected by the soldering process were performed. Results showed a yield of approximately 30% of the sensors after the reflow soldering process. The yield was also dependent on sensor placement and possibly shape. Optimization of the sensor design and placement is expected to bring the yield to 50% or better. The sensors responded as expected to impact tests. Delamination areas were present in the test PCBs, which requires further investigation. The delamination does not seem to be due to the presence of embedded sensors alone but rather the result of a combination of several factors. The conclusion of this work is that it is feasible to embed piezoelectric sensors in the layers of a PCB.

In power electronics, more efficient removal of heat from the junction of power devices leads to a higher power rating per die, which in turn leads to fewer die and reduced system volume. Since temperature is a main driver in expected failure modes an increase in cooling capability can also enhance margins of the device reliability. Previously, CFD simulations of two novel heat exchanger designs that will be used in a power module with double sided cooling have been reported on. The heat exchangers are fabricated by direct 3D manufacturing of copper structures, which allows almost complete freedom in geometric design. Two novel geometries of heat exchanger cooling structures have previously been modeled in terms of thermal performance and expected pressure drop. A flow rig has been designed and calibrated to measure thermal performance and pressure drops of these heat sinks. For calibration purposes, measurements of the thermal response of wave structured and unstructured heat sinks are reported here. The results show that, as expected, the heat sink temperatures are lower for all flow rates in the wavestructured geometry. A thermal CFO model accurately predicts the behavior of the temperature difference between inlet and outlet versus flow rate, but predicts higher absolute temperature values. It was also found that the model underestimates the pressure drop over the tested heat sillies. The pressure drop across a novel pine cone geometry heat sink fabricated by additive manufacturing methods was also measured. Comparisons to a reduced model, which neglects everything before the inlet and after the outlet of the tested device, showed that the behavior of this pine structured heat sink was not predicted correctly. The pressure drop increased more rapidly with flow rates in the model than in the measurements. The main source of error in the measurements and simulations comes from a lack of thermal loading. Future work to improve the flow rig includes possibilities to increase the temperature loading at the bottom of the heat sink under test.

Power transistors based on silicon carbide (SiC) are now commercially available. They have a higher efficiency and higher voltage blocking capabilities than conventional silicon devices. The wide-band gap and chemical inertness of SiC makes it suitable to high temperature operation. However, there is a need for new packaging for power transistors that can operate in higher temperatures. We have developed a package based on ceramics and silver for high temperature operation of SiC power transistors. Three types of SiC devices from different manufacturers are packaged and tested in room temperature. Though the devices were still functional after the packaging process, their performance seem to have degraded. This could be a result of the high temperature packaging process and the measurement setup. FEM simulations are also performed to investigate the thermo-mechanical behavior of the package. The target operating temperature of the package is 400°C. Modeling show stress concentrations at the corners of the device chip and suggests that this stress is decreased if the substrate metallization is changed from copper to silver.

Thermo-electric modules can be used to convert heat into electricity by utilizing the Seeback effect. It is now possible to buy BiTe thermo-electric modules that can operate up to temperatures of around 300°C. However, many applications, such as the harvesting of exhaust gas from large vehicles or gas turbine heat, may occur at higher temperatures Therefore, new materials and manufacturing processes need to be developed to produce packaged TEM that can operate at a maximum operating temperature of 650°C. Two critical areas in the manufacture of a SiGe TEM are the choice and strength of materials used to both solder the TE material to the rest of the module and the metal used for the interconnects. The interconnection material needs to be sufficiently strong to withstand large temperature fluctuations while maintaining a low contact resistance, as well as being compatible with the nano-Ag solder. Shear force tests of the sintered thermo electrical leg material showed that the joints are brittle when sintered to W metallized AlN substrates are used and ductile fracture behavior when sintered to Cu metallized AlN substrates using the NanoTach K nano silver paste. Almost all of the joints were found to be brittle when using the NachTach X nano silver paste. Shear testing of the solder joints showed that the X paste joints were variable in strength and stiffness, having a typical Young's modulus between 10 and 100 MPa at room temperature. The K paste joints were stiffer, but had a similar strength as compared to the X paste joints.

Thermo-electric modules (TEMs) can be used to convert heat into electricity by utilizing the Seeback effect. It is now possible to buy BiTe thermo-electric modules that can operate up to temperatures of around 300 °C. However, many applications, such as the harvesting of excess gas turbine heat, may occur at higher temperatures. Therefore, new materials and manufacturing processes need to be developed to produce packaged TEMs that can operate at a maximum operating temperature of 650 °C. Two critical areas in the manufacture of a SiGe TEM are the choice and strength of materials used to both sintered joint the TE material to the rest of the module and the metal used for the interconnects. The interconnection material needs to be sufficiently strong to withstand large temperature fluctuations while maintaining a low contact resistance, as well as being compatible with the nano-Ag sintered joint. Shear force tests of the sintered thermo electrical leg material showed that the joints are brittle when sintered to W metallized AlN substrates are used and ductile fracture behavior when sintered to Cu metallized AlN substrates using the NanoTach K nano silver paste. Almost all of the joints were found to be brittle when using the NachTach X nano silver paste. Shear testing of the sintered joints showed that the X paste joints were variable in strength and stiffness, having a typical Young's modulus between 10 and 100 MPa at room temperature. The K paste joints were stiffer, but had a similar strength as compared to the X paste joints.

To generate data used for developing schemes and models for CM, PHM, and for estimating RUL of power electronic devices, accelerated aging experiments in the form of power cycling are often performed. In these experiments, a set current is passed through the power devices and is turned on and off in regular cycles. Due to the mismatch in CTEs of the materials in the devices, the on/off cycles will generate thermally induced stress in the various material interfaces, which is the main cause of failures. Most of the power cycling setups that are currently used can only manage a single set on-state current level and fixed on/off times (which is also the common standard for lifetime testing); a condition that is very far from most real applications. The experimental setup described here is based on a Gamry Reference 3000AEpotentiostat/galvanostat/ZRA working with a Gamry 30k Booster, which can be programmed to generate a variable load current profile and will thus enable the application of more realistic conditions for accelerated aging of power electronic devices in the lab. This will improve prognostics model development and provide excellent use cases for evaluating the capabilities of the prognostics algorithms for generalization to field conditions. The application of variable load profiles from the field, instead of the regular on/off cycles traditionally used, is not compatible with the commonly used method of using the chip itself as a temperature sensor. Instead, we here present a novel method of estimating the junction temperature using a device specific derivation of thermal parameters from the measured cooling block temperature, case temperature, and dissipated power in conjunction with simulations using the PySpice simulation package implemented in Python. The setup coupled with the new junction temperature estimation is an important step in enabling predictive maintenance of power devices that is currently missing from the power electronics community. © 2024 IEEE.

The overall objective of the project wearITmed, Wearable sensors in smart textiles, is to develop a novel wearable sensor system demonstrator. This sensor system aims to monitor symptoms of neurological disorders such as epilepsy, Parkinson’s disease and stroke. The wearable sensor system demonstrator, including both integrated gyros/accelerometers and textile sensors, is useful for the evaluation of clinically relevant movement patterns and other physiological parameters, and further to establish disease discriminating and treatment responsive objective variables. The work presented in this paper is focused on ensuring that the wearable sensor system can be cleaned and washed without first removing the electronics. The work includes three main areas; the adhesion and architecture, the molding and finally the washing test performance. Standard wettability and peel tests (Volvo Standard STD 185–0001) were performed on standard test board IPC-B-5 and IPC-9202 test vehicle for selecting the best adhesive and encapsulation materials in form of an epoxy (Epotek 302–3M) and a medical approved silicone (Nusil MED-6019). The molded components were washtested (Standard SS-EN ISO 6330:2012) followed by testing of the electrical resistance (Standard IPC-9202). As a result a total of 22 garments were produced with four individually mounted boards in each garment. The tests showed that the wearable sensors passed the washing tests and were still functional after 10 repeated washing cycles without any change or degradation in resistance or sign of electrical failure. The wearable electronics therefore meets the requirements of being simultaneously resistant to; water, temperature (40 °C), chemical detergents and dynamic forces.

The substitution of lead in the electronics industry is one of the key issues in the current drive toward ecological manufacturing. This chapter is aimed at giving an overview of requirements, current situation, problems, and possible development of lead-free soldering and other environmentally friendly joining technologies. It starts with the overview of existing EU regulations and directives. The current situation in the lead-free soldering field is mapped here and a review of the literature, including a patent search, reveals systems and technologies that are at the focus of research effort. New approaches that employ the use of theoretical modeling in the development of new materials is briefly discussed in this chapter.The final part shows the difficulties that the industry faces when implementing new materials into production. The task of this part is to summarize the likely impacts of the phasing out of lead-containing solders for industry, especially small- and medium-sized enterprises.

The substitution of lead in the electronics industry is one of the key issues in the current drive towards ecological manufacturing. Legislation has already banned the use of lead in solders for mainstream applications (T M≈220 °C), but the use of lead in the solders for high-temperature applications (>85% lead, T M≈250-350 °C) is still exempt in RoHS2. The search for proper substitutes has been ongoing among solder manufacturers only for a decade without finding a viable low cost alternative and is the subject of intensive research. This article tries to map the current situation in the field of high-temperature lead-free soldering, presenting a short review of current legislation, requirements for substitute alloys, and finally it describes some existing solutions both in the field of promising new materials and new technologies. Currently, there is no drop-in replacement for lead-containing solders and therefore both the new materials and the new technologies may be viable solutions for production of reliable lead-free joints for high-temperature applications.

Lead-free solder joints have been shown to increase the risk for crack formation in the PCB laminate under the solder pads. As such cracks propagate during thermal cycling, they decrease the strain imposed on the solderjoint by acting as strain relief. In accelerated thermal cycling, these joints have been found to remain virtually undamaged even after a very high number of cycles. If these cracks do not form or propagate to the same extent under milder cycling conditions, typical of service conditions, it may lead to an overestimation of the fatigue life of the solder joints in accelerated testing. In this work, the extent of strain relief and the influence of grain orientations on the initiation and propagation of these cracks are investigated through FE-modelling and compared to what has been experimentally observed for cross-sections of solder joints moulded in epoxy resin with added fluorescent agent and inspected using UV-light and electron backscatter diffraction. Due to the strong anisotropy of lead-free solder joints, the stress transferred to the laminate will vary significantly depending on grain orientation. The presence of these laminate cracks adds another layer of uncertainty to the already complex SnAgCu system, where the strong effects of anisotropy, the continuously evolving secondary precipitate coarsening and its interaction with the recrystallisation process govern the damage evolution. If these effects are not properly accounted for, the interpretation of thermal cycling or modelling and simulation results may be strongly misleading.

The microstructure of lead-free solder joints often consists of only one or a few randomly oriented tin grains as a result of a large degree of undercooling during solidification. Due to the severe anisotropy of single crystal Sn and the random nature of the microstructure, the stress state and microstructural evolution of each joint will be unique.

Den brist på halvledare som industrin upplevt under 2021 har satt den annars tämligen anonyma halvledarindustrin i rampljuset såväl i Sverige som i Europa, USA och globalt. Hur länge denna brist kommer att bestå är en viktig fråga för industrin, som dock är svår att svara på. Enligt internationella analytiker kommer industrin att uppleva halvledarbrist fram till sommaren 2022 och eventuellt in på nästa höst eller eventuellt längre, varefter det föreligger en risk för överproduktion då lager förmodligen byggts upp bland avnämare. Erfarenheterna från tidigare halvledarbrister är att de så småningom övergår i överskott. Men den nuvarande bristen kan sannolikt kräva längre tid för detta än tidigare brister. Främsta skälet är att de halvledarfabriker som för närvarande är under uppbyggnad för att råda bot på bristen lider av samma överhettade försörjningskedjor som övrig industri, med förseningar av allt från vitala utrustningar till förbrukningsmateriel, och att det därför troligen kommer att ta längre tid än planerat att få dem i drift. Detta kan i värsta fall innebära att det rentav kan ta ett eller flera år längre tid än analytikerna förutspått innan försörjningsläget är normalt. Sverige är en del av det globala halvledarekosystemet – ett komplext ekosystem som kännetecknas av hög grad av arbetsfördelning, hög kapitalintensitet, hög kunskapsintensitet, långa produktionstider, stark internationalisering och starka inlåsningseffekter. Sverige interagerar med detta globala ekosystem på två sätt - som leverantör av produkter och tjänster i ett antal nischer där vi uppvisar global spetskompetens samt som avnämare av halvledarprodukter för industriella behov. Båda dessa sidor behöver stärkas för att a) våra SMF och stora företag ska kunna få tillgång till de halvledare och system byggda på halvledare som krävs för den produktion av produkter och tjänster som bidrar till Sveriges välstånd, b) svenska industriföretag ska kunna säkra tillgång till den kompetens och de tjänster som krävs då industrins produkter innehåller allt större mängd halvledare, och c) för att maximera möjligheterna för svenska halvledar- och elektronikinnovationer att hävda sig på världsmarknaden, och på så sätt bidra till landets välstånd. Det övergripande målet för Sverige bör vara att använda vår nationella styrka inom innovation som hävstång, och fokusera de starka specialiserade kompetenserna som finns här i landet, jämte långsiktiga investeringar i forskning inom halvledarteknik, systemdesign och halvledarmaterial, i syfte att med samlad kraft nå följande strategiska mål: 1) Etablera Sverige som ett halvledarinnovationsland genom att stärka vårt innovationssystem för halvledare och halvledarmaterial. 2) Få utväxling på de svenska investeringarna i forsknings- och innovationsinfrastruktur för design och produktion av halvledare. 3) Säkra och vidmakthåll en roll för Sverige i halvledarindustrin, inte minst genom svensk representation i de organ och församlingar som beslutar om framtida europeiska investeringar. För att nå dessa mål krävs stark samverkan mellan industri, akademi, institut och offentlig sektor, och långsiktiga såväl publika som privata investeringar i utbildning, forskningsinfrastruktur, test- och demonstrationsanläggningar och i startup- och scaleup-bolag. RISE åsikt är att Sverige därtill bör ta aktiv del i EU-initiativ som den europeiska halvledaralliansen (Alliance on Processor and Semiconductor Technologies) och European Chips Act. Påpekas bör att dessa mål är långsiktiga och kräver kontinuerligt arbete och finansiering under många år framöver. De löser inte industrins kortsiktiga behov av halvledare, och det kommer att ta tid att säkra industrins behov av halvledarkompetens. Med en väl genomförd strategi skulle dock dessa behov i högre grad kunna tillgodoses samtidigt som vårt lands bidrag till det globala halvledarekosystemet skulle växa kraftigt, till fromma för vårt gemensamma välstånd.

Unified Modelling Language (UML) has a graphical notation for 13 different types of diagrams and can be used as a general modelling tool. Well-known examples of diagram types are class diagrams for modelling classes that can be instanced into objects, state machine diagrams for modelling states in systems and activity diagrams for modelling process flows. A literature survey shows that UML has been used to model concepts and methodologies of risk assessment and risk management. One example is the Coras Framework. The international standard CEI IEC 61882 Hazard and operability (HAZOP) studies describes concepts for investigating and detecting possible hazards in systems. In CEI IEC 6882, guide words like More and Less are applied to system parameters to invoke deviations in the system and assess possible hazards due to the deviation from the design intent. In this paper, we have used UML to model concepts of CEI IEC 61882 Hazards and operability studies. Diagrams of UML were used to show dependencies and relations between parts of the target system and concepts of CEI IEC 61882. Extensions of UML are suggested to better capture and display the concepts of CEI IEC 61882, the results of a HAZOP study and emerging risk. These extensions are referred to as UML for emerging risks (UML-ER).

In this paper, the effects of the input signal power on microwave planar devices are studied in detail. In this context, a complete multiphysics study is performed, involving the electro-thermo-mechanical coupling in microwave components. For this study, a multiphysics simulator is used. As shown, for moderate input powers, the device transfer function can be altered, mainly in terms of an increase of losses and a frequency shift. Additionally, hot spots are to be appeared, whose location is related to the electromagnetic field distribution of the passive device under test. Guidelines are also provided to estimate the average power handling capability (APHC) of planar components. As an example, the multiphysics analysis of a microstrip coupled-line filter centered at 42 GHz is tackled taken into account different thermal and mechanical boundary conditions.

Remaining useful life prediction models are a central aspect of developing modern and capable prognostics and health management systems. Recently, such models are increasingly data-driven and based on various machine learning techniques, in particular deep neural networks. Such models are notoriously “data hungry”, i.e., to get adequate performance of such models, a substantial amount of diverse training data is needed. However, in several domains in which one would like to deploy data-driven remaining useful life models, there is a lack of data or data are distributed among several actors. Often these actors, for various reasons, cannot share data among themselves. In this paper a method for collaborative training of remaining useful life models based on federated learning is presented. In this setting, actors do not need to share locally held secret data, only model updates. Model updates are aggregated by a central server, and subsequently sent back to each of the clients, until convergence. There are numerous strategies for aggregating clients’ model updates and in this paper two strategies will be explored: 1) federated averaging and 2) federated learning with personalization layers. Federated averaging is the common baseline federated learning strategy where the clients’ models are averaged by the central server to update the global model. Federated averaging has been shown to have a limited ability to deal with non-identically and independently distributed data. To mitigate this problem, federated learning with personalization layers, a strategy similar to federated averaging but where each client is allowed to append custom layers to their local model, is explored. The two federated learning strategies will be evaluated on two datasets: 1) run-to-failure trajectories from power cycling of silicon-carbide metal-oxide semiconductor field-effect transistors, and 2) C-MAPSS, a well-known simulated dataset of turbofan jet engines. Two neural network model architectures commonly used in remaining useful life prediction, long short-term memory with multi-layer perceptron feature extractors, and convolutional gated recurrent unit, will be used for the evaluation. It is shown that similar or better performance is achieved when using federated learning compared to when the model is only trained on local data.