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  • 1.
    Akbari, Saeed
    et al.
    RISE Research Institutes of Sweden, Digital Systems, Smart Hardware.
    Kostov, Konstantin Stoychev
    RISE Research Institutes of Sweden, Digital Systems, Smart Hardware.
    Brinkfeldt, Klas
    RISE Research Institutes of Sweden, Digital Systems, Smart Hardware.
    Adolfsson, Erik
    RISE Research Institutes of Sweden, Materials and Production, Manufacturing Processes.
    Lim, Jang-Kwon
    RISE Research Institutes of Sweden, Digital Systems, Smart Hardware.
    Andersson, Dag
    RISE Research Institutes of Sweden, Digital Systems, Smart Hardware.
    Bakowski, Mietek
    RISE Research Institutes of Sweden, Digital Systems, Smart Hardware.
    Wang, Qin
    RISE Research Institutes of Sweden, Digital Systems, Smart Hardware.
    Salter, Michael
    RISE Research Institutes of Sweden, Digital Systems, Smart Hardware.
    Ceramic Additive Manufacturing Potential for Power Electronics Packaging2022In: IEEE Transactions on Components, Packaging, and Manufacturing Technology, ISSN 2156-3950, E-ISSN 2156-3985, Vol. 12, no 11, p. 1857-1866Article in journal (Refereed)
    Abstract [en]

    Compared with silicon-based power devices, wide band gap (WBG) semiconductor devices operate at significantly higher power densities required in applications such as electric vehicles and more electric airplanes. This necessitates development of power electronics packages with enhanced thermal characteristics that fulfil the electrical insulation requirements. The present research investigates the feasibility of using ceramic additive manufacturing (AM), also known as three-dimensional (3D) printing, to address thermal and electrical requirements in packaging gallium nitride (GaN) based high-electron-mobility transistors (HEMTs). The goal is to exploit design freedom and manufacturing flexibility provided by ceramic AM to fabricate power device packages with a lower junction-to-ambient thermal resistance (<italic>R</italic>&#x03B8;JA). Ceramic AM also enables incorporation of intricate 3D features into the package structure in order to control the isolation distance between the package source and drain contact pads. Moreover, AM allows to fabricate different parts of the packaging assembly as a single structure to avoid high thermal resistance interfaces. For example, the ceramic package and the ceramic heatsink can be printed as a single part without any bonding layer. Thermal simulations under different thermal loading and cooling conditions show the improvement of thermal performance of the package fabricated by ceramic AM. If assisted by an efficient cooling strategy, the proposed package has the potential to reduce <italic>R</italic>&#x03B8;JA by up to 48%. The results of the preliminary efforts to fabricate the ceramic package by AM are presented, and the challenges that have to be overcome for further development of this manufacturing method are recognized and discussed. 

  • 2.
    Bakowski, Mietek
    et al.
    RISE, Swedish ICT, Acreo.
    Lim, Jang-Kwon
    RISE, Swedish ICT, Acreo.
    Kaplan, W
    Merits of Buried Grid Technology for SiC JBS Diodes2012In: ECS Transactions, ISSN 1938-5862, E-ISSN 1938-6737, Vol. 50, no 3, p. 415-424Article in journal (Refereed)
  • 3.
    Bakowski, Mietek
    et al.
    RISE, Swedish ICT, Acreo.
    Lim, Jang-Kwon
    RISE, Swedish ICT, Acreo.
    Kaplan, W
    Schöner, A
    Merits of buried grid technology for advanced SiC device concepts2011In: ECS Transactions, ISSN 1938-5862, E-ISSN 1938-6737, Vol. 41, no 8, p. 155-62Article in journal (Refereed)
  • 4.
    Bakowski, Mietek
    et al.
    RISE, Swedish ICT, Acreo.
    Lim, Jang-Kwon
    RISE, Swedish ICT, Acreo.
    Kaplan, Wlodek
    RISE, Swedish ICT, Acreo.
    Merits of Buried Grid Technology for SiC JBS Diodes2012In: GALLIUM NITRIDE AND SILICON CARBIDE POWER TECHNOLOGIES 2, 2012, Vol. 50, p. 415-424Conference paper (Refereed)
    Abstract [en]

    The SiC Schottky barrier diodes for 200 degrees C to 250 degrees C operation have been developed using buried grid (BG) technology. 2A and 10A, 1700V BG JBS diodes have been fabricated and evaluated. Manufactured 10A, 1700V BG JBS diodes have leakage current at least three orders of magnitude lower compared to the typical data sheet values of the commercial devices. The leakage current at 250 degrees C is of the same order of magnitude as that of the commercial devices at 175 degrees C. The two alternative technologies for realization of BG, implantation and epitaxy, have been compared by simulations. The epitaxial grid is shown to have superior potential for best trade-off between on-state voltage and leakage current.

  • 5.
    Bakowski, Mietek
    et al.
    RISE, Swedish ICT, Acreo.
    Ranstad, P.
    Alstom Power Sweden AB, Sweden.
    Lim, Jang-Kwon
    RISE, Swedish ICT, Acreo.
    Kaplan, Wlodek
    RISE, Swedish ICT, Acreo. Ascatron AB, Sweden.
    Reshanov, Sergey
    RISE, Swedish ICT, Acreo. Ascatron AB, Sweden.
    Schoner, Adolf
    RISE, Swedish ICT, Acreo. Ascatron AB, Sweden.
    Giezendanner, F.
    Alstom Power Sweden AB, Sweden.
    Ranstad, A.
    Alstom Power Sweden AB, Sweden.
    Design and characterization of newly developed 10 kV 2 A SiC p-i-n diode for soft-switching industrial power supply2015In: IEEE Transactions on Electron Devices, ISSN 0018-9383, E-ISSN 1557-9646, Vol. 62, no 2, p. 366-373Article in journal (Refereed)
    Abstract [en]

    10 kV, 2 A SiC p-i-n diodes have been designed and fabricated. The devices feature excellent stability of forward characteristics and robust junction termination with avalanche capability of 1 J. The fabricated diodes have been electrically evaluated with respect to dynamic ON-state voltage, reverse recovery behavior, bipolar stability, and avalanche capability. More than 60% reduction of losses has been demonstrated using newly developed 10-kV p-i-n diodes in a multikilowatt high voltage, high-frequency dc/dc soft-switching converter

  • 6.
    Belov, Ilia
    et al.
    Jönköping University, Sweden.
    Lang, Jenny
    RISE, SP – Sveriges Tekniska Forskningsinstitut.
    Hellén, Johan
    Saab AB, Sweden.
    Lim, Jang-Kwon
    RISE, Swedish ICT, Acreo.
    Schødt, Bo
    RISE, SP – Sveriges Tekniska Forskningsinstitut.
    Nilsson, Torbjörn M. J.
    Saab AB, Sweden.
    Poder, Ralf
    RISE, SP – Sveriges Tekniska Forskningsinstitut.
    Bakowski, Mietek
    RISE, Swedish ICT, Acreo.
    Leisner, Peter
    RISE, SP – Sveriges Tekniska Forskningsinstitut.
    Reliability study of GaN HEMTs2016Conference paper (Other academic)
  • 7.
    Elahipanah, H.
    et al.
    Ascatron AB, Sweden.
    Thierry-Jebali, N.
    Ascatron AB, Sweden.
    Reshanov, S. A.
    Ascatron AB, Sweden.
    Kaplan, W.
    Ascatron AB, Sweden.
    Zhang, A.
    Ascatron AB, Sweden.
    Lim, Jang-Kwon
    RISE - Research Institutes of Sweden (2017-2019), ICT, Acreo.
    Bakowski, Mietek
    RISE - Research Institutes of Sweden (2017-2019), ICT, Acreo.
    Östling, M.
    KTH Royal Institute of Technology, Sweden.
    Schöner, A.
    Ascatron AB, Sweden.
    Design optimization of a high temperature 1.2 kV 4H-SiC buried grid JBS rectifier2017In: 11th European Conference on Silicon Carbide and Related Materials, ECSCRM 2016, 2017, p. 455-458Conference paper (Refereed)
    Abstract [en]

    1.2 kV SiC buried grid junction barrier Schottky (BG-JBS) diodes are demonstrated. The design considerations for high temperature applications are investigated. The design is optimized in terms of doping concentration and thickness of the epilayers, as well as grid size and spacing dimensions, in order to obtain low on-resistance and reasonable leakage current even at high temperatures. The device behavior at temperatures ranging from 25 to 250ºC is analyzed and measured on wafer level. The forward voltage drop of 1.1 V at 100 A/cm2 and 3.8 V at 1000 A/cm2 is measured, respectively. At reverse voltage of 1 kV, a leakage current density below 0.1 μA/cm2 and below 0.1 mA/cm2 is measured at 25 and 250ºC, respectively. This proves the effective shielding effect of the BG-JBS design and provides benefits in high voltage applications, particularly for high temperature operation.

  • 8.
    Kostov, Konstantin Stoychev
    et al.
    RISE, Swedish ICT, Acreo.
    Lim, Jang-Kwon
    RISE, Swedish ICT, Acreo.
    Zhang, Yafan Fan
    RISE, Swedish ICT, Acreo.
    Bakowski, Mietek
    RISE, Swedish ICT, Acreo.
    Impact of package parasitics on switching performance2016In: Materials Science Forum, 2016, Vol. 858, p. 1057-1060Conference paper (Refereed)
    Abstract [en]

    The package parasitics are a serious obstacle to the high-speed switching, which is necessary in order to reduce the switching power losses or reduce the size of power converters. In order to design new packages suitable for Silicon Carbide (SiC) power transistors, it is necessary to extract the parasitics of different packages and be able to predict the switching performance of the power devices placed in these packages. This paper presents two ways of simulating the switching performance in a half-bridge power module with SiC MOSFETs. The results show that the parasitic inductances in the power module slow down the switching, lead to poor current sharing, and together with the parasitic capacitances lead to oscillations. These negative effects can cause failures, increased losses, and electromagnetic compatibility issues.

  • 9.
    Lang, Jenny
    et al.
    RISE, SP – Sveriges Tekniska Forskningsinstitut, SP Elektronik.
    Belov, Ilia
    Jönköping University, Sweden.
    Hellén, Johan
    Saab AB, Sweden.
    Lim, Jang-Kwon
    RISE, Swedish ICT, Acreo.
    Schødt, Bo
    RISE, SP – Sveriges Tekniska Forskningsinstitut.
    Nilsson, Torbjörn M. J.
    Saab AB, Sweden.
    Poder, Ralf
    RISE, SP – Sveriges Tekniska Forskningsinstitut, SP Elektronik.
    Bakowski, Mietek
    RISE, Swedish ICT, Acreo.
    Leisner, Peter
    RISE - Research Institutes of Sweden (2017-2019), Safety and Transport, Electronics. Jönköping University, Sweden.
    Thermo-Mechanical Reliability and Performance Degradation of a Lead-Free RF Power Amplifier with GaN-on-SiC HEMTs2016In: Materials Science Forum, 2016, Vol. 897, no May, p. 715-718Conference paper (Refereed)
    Abstract [en]

    RF power amplifier demonstrators containing each one GaN-on-SiC, HEMT, CHZ015AQEG, from UMS in SMD quad-flat no-leads package (QFN) were subjected to thermal cycles (TC) and power cycles (PC) followed by electrical, thermal and structural evaluation. Two types of solders i.e. Sn63Pb36Ag2 and lead-free SnAgCu (SAC305) and two types of TIM materials (NanoTIM and TgonTM 805) for PCB attachment to liquid cold plate were tested for thermomechanical reliability. Changes in electrical performance of the devices namely reduction of the current saturation value, threshold voltage shift, increase of the leakage current and degradation of the HF performance were observed as a result of an accumulated current stress during PC. No significant changes in the investigated solder or TIM materials were observed. 

  • 10.
    Lang, Jenny
    et al.
    RISE, SP – Sveriges Tekniska Forskningsinstitut.
    Lim, Jang-Kwon
    RISE, Swedish ICT, Acreo.
    Hellén, Johan
    Saab AB, Sweden.
    Nilsson, Torbjörn M. J.
    Saab AB, Sweden.
    Schodt, Bo
    RISE, SP – Sveriges Tekniska Forskningsinstitut.
    Poder, Ralf
    RISE, SP – Sveriges Tekniska Forskningsinstitut.
    Belov, Ilja
    Jönköping University, Sweden.
    Bakowski, Mietek
    RISE, Swedish ICT, Acreo.
    Leisner, Peter
    RISE, SP – Sveriges Tekniska Forskningsinstitut.
    Reliability study of a RF power amplifier with GaN-on-SiC HEMTs2016In: ECS Transactions, 2016, Vol. 75, no 12, p. 49-59Conference paper (Refereed)
    Abstract [en]

    RF power amplifier demonstrators containing each one GaN-on- SiC, HEMT, CHZ015A-QEG, from UMS in SMD quad-flat noleads package (QFN) were subjected to thermal cycles (TC) and power cycles (PC) and evaluated electrically, thermally and structurally. Two types of lead-free solders (Sn63Pb36Ag2 and SnAgCu (SAC305)) and two types of TIM materials (NanoTIM and TgonTM 805) for PCB attachment to liquid cold plate were tested for thermo-mechanical reliability. Changes in electrical performance of the devices namely reduction of the current saturation value, threshold voltage shift, increase of the leakage current and degradation of the HF performance were observed as a result of an accumulated current stress during PC. No significant changes in the investigated solder or TIM materials were observed.

  • 11.
    Lang, Jenny
    et al.
    RISE - Research Institutes of Sweden (2017-2019), Safety and Transport, Electronics.
    Lim, Jang-Kwon
    RISE - Research Institutes of Sweden (2017-2019), ICT, Acreo.
    Hellén, Johan
    Saab AB, Sweden..
    Nilsson, Torbjörn M.J.
    Saab AB, Sweden..
    Schödt, Bo
    RISE, SP – Sveriges Tekniska Forskningsinstitut, SP Danmark A/S.
    Poder, Ralf
    RISE, SP – Sveriges Tekniska Forskningsinstitut, SP Danmark A/S.
    Belov, Ilja
    Jönköping University, Sweden.
    Bakowski, Mietek
    RISE - Research Institutes of Sweden (2017-2019), ICT, Acreo.
    Leisner, Peter
    RISE - Research Institutes of Sweden (2017-2019), Safety and Transport, Electronics.
    Reliability Study of GaN-onSiC HEMT RF Power Amplifiers2018In: Advances in Technology Innovation, Vol. 3, no 4, p. 157-165Article in journal (Refereed)
    Abstract [en]

    The RF power amplifier demonstrators containing each one GaN-on-SiC, HEMT, CHZ015A-QEG, from UMSin SMD quad-flat no-leads package (QFN) were subjected to thermal cycles (TC) and power cycles (PC) andevaluated electrically, thermally and structurally. Two types of solders, Sn63Pb36Ag2 and lead-free SnAgCu(SAC305), and two types of TIM materials, NanoTIM and TgonTM 805, for PCB attachment to the liquid cold platewere tested for thermo-mechanical reliability. Changes in the electrical performance of the devices, namely thereduction of the current saturation value, threshold voltage shift, increase of the leakage current and degradation ofthe HF performance were observed as a result of an accumulated current stress during PC. No significant changes inthe investigated solder or TIM materials were observed.

  • 12.
    Lee, Geon Hee
    et al.
    Kwangwoon University, Republic of Korea.
    Lim, Jang-Kwon
    RISE Research Institutes of Sweden, Digital Systems, Smart Hardware.
    Koo, Sang Mo
    Kwangwoon University, Republic of Korea.
    Bakowski, Mietek
    RISE Research Institutes of Sweden, Digital Systems, Smart Hardware.
    Measurement and Analysis of Body Diode Stress of 3.3 kV Sic-Mosfets with Intrinsic Body Diode and Embedded SBD2023In: Materials Science Forum, ISSN 0255-5476, E-ISSN 1662-9752, Vol. 1091, p. 55-59Article in journal (Refereed)
    Abstract [en]

    SiC MOSFETs display reliability issues related to the quality of SiO2/SiC interface and bulk material due to the presence of near interface traps and point and extended material defects [1]. These material related issues give rise to a degradation of device reliability and ruggedness. One of them are basal plane dislocations (BPDs) introduced in the drift-layer during the epitaxial growth process which causes a s.c. bipolar degradation. Growth and movement of BPDs fueled by recombination energy has a very significant impact on conduction loss and on-resistance degradation. For 3.3 kV voltage capability, the probability of the appearance of BPDs is greater because the drift region is about three times larger compared to 1.2 kV devices [2-3]. We present measurement results and analysis of bipolar degradation in 3.3 kV MOSFETs with conventional body diode and embedded schottky barrier diode (SBD). The measurements were performed applying 50 % and 80 % of rated current with duty cycle 80 %, under total time of 100 hrs at constant case temperature of 54 °C. The 3rd-quadrant performance of both types of MOSFETs in pre-stress conditions was characterized at 25 and 150 °C with different gate biases of -10 V, 0 V, and +17 V. To evaluate the bipolar degradation, the diode conduction characteristics were measured at 25 °C after different stressing times by diode conduction the MOSFET output characteristics were measured at 25 and 54 °C before and after stressing the intrinsic body diode and embedded SBD. No VSD shift was observed in diode conduction characteristics. The results indicate that the MOSFETs were fabricated on appropriate material with a sufficiently low number basal plane dislocation (BPD). The on-state resistance with VGS = +17 V was decreased by temperature due to increased JFET resistance rather than bipolar degradation. On the other hand, the on-state resistance with VGS = +11 V was impacted by the increased temperature and VTH instability.

  • 13.
    Lim, Jang-Kwon
    et al.
    RISE, Swedish ICT, Acreo.
    Bakowski, Mietek
    RISE, Swedish ICT, Acreo.
    Nee, H-P
    Design gate drive considerations for epitaxial 1.2kV buried grid N-on N-off JFETs for operation at 250C2010In: Materials Science Forum, ISSN 0255-5476, E-ISSN 1662-9752, Vol. 645-648, p. 961-Article in journal (Refereed)
  • 14.
    Lim, Jang-Kwon
    et al.
    RISE, Swedish ICT, Acreo. KTH Royal Institute of Technology, Sweden.
    Peftitsis, Dimosthenis
    KTH Royal Institute of Technology, Sweden.
    Rabkowski, Jacek
    Warsaw University of Technology, Poland; KTH Royal Institute of Technology, Sweden.
    Bakowski, Mietek
    RISE, Swedish ICT, Acreo.
    Nee, Hans Peter
    KTH Royal Institute of Technology, Sweden.
    Analysis experimental verification of the influence of fabrication process tolerances circuit parasitic on transient current sharing of parallel-connected SiC JFETs2014In: IEEE transactions on power electronics, ISSN 0885-8993, E-ISSN 1941-0107, Vol. 29, no 5, p. 2180-91Article in journal (Refereed)
    Abstract [en]

    Operation of parallel-connected 4H-SiC vertical junction field effect transistors (VJFETs) from SemiSouth is modeled using numerical simulations and experimentally verified. The unbalanced currentwaveforms of parallel-connected VJFETs are investigated with respect to the spread in the critical parameters of the device structure and to the influence of the parasitic inductances in the measurement circuit. The device structures are reconstructed based on scanning electron microscopy (SEM) analysis, electrical characterization, and device simulations. The doping concentration and profile depth of a p-grid formed by angular implantation are studied as main contributors that influence the variation of the on-state characteristics, and the threshold voltage of the experimentaldevices. It has been shown elsewhere that similar differences in p-grid also lead to differences in gate-source breakdown voltage. The switching performance of the parallel-connected JFETs is measured using single and double gate drivers in a double-pulse test and compared with simulations. The switched current and voltage waveforms from measurements are reproduced in simulation by introducing the parasitics. From the analysis, it is found that reasonable differences in doping levels and profiles of the p-grid give rise to significant differences in device parameters. However, even with these parameter differences and circuit asymmetries, it is possible to successfully operate parallel-connected VJFETs of this type.

  • 15.
    Lim, Jang-Kwon
    et al.
    RISE, Swedish ICT, Acreo. RISE Research Institutes of Sweden, Digital Systems, Smart Hardware.
    Peftitsis, Dimosthenis
    KTH Royal Institute of Technology, Sweden.
    Rabkowski, Jacek
    KTH Royal Institute of Technology, Sweden.
    Bakowski, Mietek
    RISE, Swedish ICT, Acreo.
    Nee, Hans-Peter
    KTH Royal Institute of Technology, Sweden.
    Modeling of the impact of parameter spread on the switching performance of parallel-connected SiC VJFETs2013In: Materials Science Forum, Trans Tech Publications Inc. , 2013, Vol. 740-742, p. 1098-1102Conference paper (Refereed)
    Abstract [en]

    Operation of parallel-connected 4H-SiC VJFETs from SemiSouth was measured and modeled using numerical simulations. The unbalanced current waveforms in parallel-connected VJFETs were related to spread in the critical parameters of the device structure and to the influence of the parasitic inductances in the measurement circuit. The physical device structure was reconstructed based on SEM analysis, electrical characterization, and device simulations. The two hypothetical critical design parameters that were studied with respect to spread were the p-gate doping profile (Case 1) and the emitter doping (Case 2). Variation in both parameters could be related to variation in the emitter breakdown voltage, the on-state characteristics, and the threshold voltage of the experimental devices. The switching performance of the parallel-connected JFETs was measured using a single gate driver in a double pulse test and compared with simulations. In both investigated cases a very good agreement between measurements and simulations was obtained. The modeling of the transient performance relies on good reproduction of transfer characteristics and circuit parasitics.

  • 16.
    Lim, Jang-Kwon
    et al.
    RISE, Swedish ICT, Acreo. KTH Royal Institute of Technology, Sweden.
    Peftitsis, Dimosthenis
    KTH Royal Institute of Technology, Sweden.
    Sadik, Diane-Perle
    KTH Royal Institute of Technology, Sweden.
    Bakowski, Mietek
    RISE, Swedish ICT, Acreo.
    Nee, Hans-Peter
    KTH Royal Institute of Technology, Sweden.
    Evaluation of buried grid JBS diodes2014In: 15th International Conference on Silicon Carbide and Related Materials, ICSCRM 2013, Trans Tech Publications Inc. , 2014, Vol. 778-780, p. 804-807Conference paper (Refereed)
    Abstract [en]

    The 4H-SiC Schottky barrier diodes for high temperature operation over 200 °C have been developed using buried grids formed by implantation. Compared to a conventional JBS-type SBD with surface grid (SG), JBS-type SBD with buried grid (BG) has significantly reduced leakage current at reverse bias due to a better field shielding of the Schottky contact. By introducing the BG technology, the 1.7 kV diodes with an anode area 0.0024 cm2 (1 A) and 0.024 cm2 (10 A) were successfully fabricated, encapsulated in TO220 packages, and electrically evaluated. Two types of buried grid arrangement with different grid spacing dimensions were investigated. The measured IV characteristics were compared with simulation. The best fit was obtained with an active area of approximately 60% and 70% of the anode area in large and small devices, respectively. The measured values of the device capacitances were 1000 pF in large devices and 100 pF in small devices at zero bias. The capacitance values are proportional to the device area. The recovery behavior of big devices was measured in a double pulse tester and simulated. The recovery charge, Qc, was 18 nC and 24 nC in simulation and measurement, respectively. The fabricated BG JBS-type SBDs have a smaller maximum reverse recovery current compared to the commercial devices. No influence of the different grid spacing on the recovery charge was observed.

  • 17.
    Lim, Jang-Kwon
    et al.
    RISE, Swedish ICT, Acreo. KTH Royal Institute of Technology, Sweden.
    Reshanov, Sergey A.
    Ascatron AB, Sweden.
    Kaplan, Wlodek
    Ascatron AB, Sweden.
    Zhang, Andy Zhenzhong
    Ascatron AB, Sweden.
    Hjort, Tomas
    Ascatron AB, Sweden.
    Schöner, Adolf
    Ascatron AB, Sweden.
    Bakowski, Mietek
    RISE, Swedish ICT, Acreo.
    Nee, Hans-Peter
    KTH Royal Institute of Technology, Sweden.
    Temperature-dependent characteristics of 4H-SiC buried grid JBS diodes2015In: Materials Science Forum, 2015, Vol. 821-823, p. 600-603Conference paper (Refereed)
    Abstract [en]

    4H-SiC Schottky Barrier Diodes (SBD) have been developed using p-type buried grids (BGs) formed by Al implantation. In order to reduce on-state resistance and improve forward conduction, the doping concentration of the channel region between the buried grids was increased. The fabricated diodes were encapsulated with TO-254 packages and electrically evaluated. Experimental forward and reverse characteristics were measured in the temperature range from 25 °C to 250 °C. On a bare die level, the forward voltage drop was reduced from 5.36 V to 3.90 V at 20 A as the channel doping concentration was increased in order to reduce the channel resistance. After encapsulation in a TO-254 package, the forward voltage drop was decreased by approximately 10% due to a lower contact resistance. The on-state resistance of an identical device measured on the bare die and in the TO-254 package increased with increasing temperature due to the decreased electron mobility in the drift region resulting in higher resistance. The incremental contact resistances of the bare dies were larger than in the packaged devices. One key issue associated with conventional Junction Barrier Schottky (JBS) diodes is a high leakage current at high temperature operation over 200 °C. The developed Buried Grid JBS (BG JBS) diode has significantly reduced leakage current due to a better field shielding at the Schottky contact. The leakage current of the packaged BG JBS diodes is compared to conventional SBD and commercial JBS diodes.

  • 18.
    Lim, Jang-Kwon
    et al.
    RISE - Research Institutes of Sweden (2017-2019), ICT, Acreo.
    Tolstoy, G
     Peftitsis, D
    Rabkowski, J
    Bakowski, Mietek
    RISE, Swedish ICT, Acreo.
    Nee, H-P
    KTH Royal Institute of Technology, Sweden.
    Comparison of total losses of 1.2kV SiC JFET BJT in DC-DC converter including gate driver2011In: Materials Science Forum, ISSN 0255-5476, E-ISSN 1662-9752, Vol. 679-80, p. 649-52Article in journal (Refereed)
  • 19.
    Lim, Jang-Kwon
    et al.
    RISE, Swedish ICT, Acreo.
    Åstlund, Ludwig
    Wang, Qin
    RISE, Swedish ICT, Acreo.
    Kaplan, Wlodek
    Reshanov, SA
    Schöner, Adolf
    Bakwoski, Mietek
    Nee, H-P
    A theoretical experimental comparison of 4H- 6H-SiC MSM UV photodetectors2012In: Materials Science Forum, ISSN 0255-5476, E-ISSN 1662-9752, Vol. 717-720, p. 1207-10Article in journal (Refereed)
  • 20.
    Lim, Jang-Kwon
    et al.
    RISE, Swedish ICT, Acreo. KTH, Elektrisk energiomvandling.
    Östlund, Ludwig
    RISE, Swedish ICT, Acreo.
    Wang, Qin
    RISE, Swedish ICT, Acreo.
    Kaplan, Wlodek
    RISE, Swedish ICT, Acreo.
    Reshanov, Sergey A.
    RISE, Swedish ICT, Acreo.
    Schöner, Adolf
    RISE, Swedish ICT, Acreo.
    Bakowski, Mietek
    RISE, Swedish ICT, Acreo.
    Nee, Hans-Peter
    RISE, Swedish ICT, Acreo. KTH, Elektrisk energiomvandling.
    A theoretical and experimental comparison of 4H- and 6H-SiC MSM UV photodetectors2012In: Silicon Carbide and Related Materials 2011, Trans Tech Publications Inc. , 2012, p. 1207-1210Conference paper (Refereed)
    Abstract [en]

    This paper reports on fabrication and modeling of 4H- and 6H-SiC metal-semiconductor-metal (MSM) photodetectors (PDs). MSM PDs have been fabricated on 4H-SiC and 6H-SiC epitaxial layers, and their performance analyzed by MEDICI simulation and measurements. The simulations were also used to optimize the sensitivity by varying the width and spacing of the interdigitated electrodes. The fabricated PDs with 2 ÎŒm wide metal electrodes and 3 ÎŒm spacing between the electrodes exhibited, under UV illumination, a peak current to dark current ratio of 10 5 and 10 4 in 4H-SiC and 6H-SiC, respectively. The measured spectral responsivity of 6H-SiC PDs was higher compared to that of 4H-SiC PDs, with a cutoff at 407 nm compared to 384 nm in 4H-SiC PDs. Also the peak responsivity occurred at a shorter wavelength in 6H material. A high rejection ratio between the photocurrent and dark current was found in both cases. These experimental results were in agreement with simulation.

  • 21.
    Nee, Hans Peter
    et al.
    KTH Royal Institute of Technology, Sweden.
    Rabkowski, Jacek
    KTH Royal Institute of Technology, Sweden.
    Peftitsis, Dimosthenis
    KTH Royal Institute of Technology, Sweden.
    Tolstoy, Georg
    KTH Royal Institute of Technology, Sweden.
    Colmenares, Juan
    KTH Royal Institute of Technology, Sweden.
    Sadik, Diane Perle
    KTH Royal Institute of Technology, Sweden.
    Bakowski, Mietek
    RISE, Swedish ICT, Acreo.
    Lim, Jang-Kwon
    RISE, Swedish ICT, Acreo.
    Antonopoulos, Antonios
    KTH Royal Institute of Technology, Sweden.
    Ängquist, Lennart
    KTH Royal Institute of Technology, Sweden.
    Zdanowski, Mariusz
    Warsaw University of Technology, Poland.
    High-Efficiency Power Conversion Using Silicon Carbide Power Electronics2014In: Materials Science Forum, ISSN 0255-5476, E-ISSN 1662-9752, Vol. 778-780Article in journal (Refereed)
    Abstract [en]

    The message of this paper is that the silicon carbide power transistors of today are good enough to design converters with efficiencies and switching speeds beyond comparison with corresponding technology in silicon. This is the time to act. Only in the highest power range the devices are missing. Another important step towards high powers is to find new solutions for multichip circuit designs that are adapted to the high possible switching speeds of unipolar silicon carbide power transistors.

  • 22.
    Nee, Hans-Peter
    et al.
    KTH Royal Institute of Technology, Sweden.
    Rabkowski, Jacek
    KTH Royal Institute of Technology, Sweden.
    Peftitsis, Dimosthenis
    KTH Royal Institute of Technology, Sweden.
    Tolstoy, Georg
    KTH Royal Institute of Technology, Sweden.
    Colmenares, Juan
    KTH Royal Institute of Technology, Sweden.
    Sadik, Diane
    KTH Royal Institute of Technology, Sweden.
    Bakowski, Mietek
    RISE, Swedish ICT, Acreo.
    Lim, Jang-Kwon
    RISE, Swedish ICT, Acreo.
    Antonopoulos, Antonios
    KTH Royal Institute of Technology, Sweden.
    Ängquist, Lennart
    KTH Royal Institute of Technology, Sweden.
    Zdanowski, Mariusz
    Warsaw University of Technology, Poland.
    High-Efficiency Power Conversion Using Silicon Carbide Power Electronics2013In: Proc. of International Conference on silicon carbide and related materials (ICSCRM) 2013, Miyazaki, Japan, Sept. 29–Oct. 4, 2013, Trans Tech Publications Inc. , 2013, p. 1083-1088Conference paper (Refereed)
    Abstract [en]

    The message of this paper is that the silicon carbide power transistors of today are good enough to design converters with efficiencies and switching speeds beyond comparison with corresponding technology in silicon. This is the time to act. Only in the highest power range the devices are missing. Another important step towards high powers is to find new solutions for multi-chip circuit designs that are adapted to the high possible switching speeds of unipolar silicon carbide power transistors.

  • 23. Peftitsis, D
    et al.
    Tolstoy, G
    Antonopoulos, A
    Rabkowski, J
    Lim, Jang-Kwon
    RISE, Swedish ICT, Acreo.
    Bakowski, Mietek
    RISE, Swedish ICT, Acreo.
    Anqquist, L
    Nee, H-P
    High-power modular multilevel converters with SiC JFETs2012In: IEEE transactions on power electronics, ISSN 0885-8993, E-ISSN 1941-0107, Vol. 27, no 1, p. 28-36Article in journal (Refereed)
  • 24.
    Peftitsis, Dimosthenis
    et al.
    KTH Royal Institute of Technology, Sweden.
    Lim, Jang-Kwon
    RISE, Swedish ICT, Acreo. KTH Royal Institute of Technology, Sweden.
    Rabkowski, Jacek
    KTH Royal Institute of Technology, Sweden.
    Tolstoy, Georg
    KTH Royal Institute of Technology, Sweden.
    Nee, Hans Peter
    KTH Royal Institute of Technology, Sweden.
    Experimental comparison of different gate-driver configurations for parallel-connection of normally-on SiC JFETs2012In: Conference Proceedings - 2012 IEEE 7th International Power Electronics and Motion Control Conference - ECCE Asia, IPEMC 2012, 2012, p. 16-22, article id 6258832Conference paper (Refereed)
    Abstract [en]

    Due to the low current ratings of the currently available silicon carbide (SiC) switches they cannot be employed in high-power converters. Thus, it is necessary to parallel-connect several switches in order to reach higher current ratings. This paper presents an investigation of parallel-connected normally-on SiC junction field effect transistors. There are four crucial parameters affecting the effectiveness of the parallel-connected switches. However, the pinch-off voltage and the reverse breakdown voltage of the gates seem to be the most important parameters which affect the switching performance of the devices. In particular, the spread in these two parameters might affect the stable off-state operation of the switches. The switching performance and the switching losses of a pair of parallel-connected devices having different reverse breakdown voltages of the gates is investigated by employing three different gate-driver configurations. It is experimentally shown that using a single gate-driver circuit the switching performance of the parallel-connected devices is almost identical, while the total switching losses are lower compared to the other two configurations.

  • 25.
    Peftitsis, Dimosthenis
    et al.
    KTH, Elektrisk energiomvandling.
    Tolstoy, Georg
    KTH, Elektrisk energiomvandling.
    Antonopoulos, Antonios
    KTH, Elektrisk energiomvandling.
    Rabkowski, Jacek
    KTH, Elektrisk energiomvandling.
    Lim, Jang-Kwon
    KTH, Elektrisk energiomvandling.
    Bakowski, Mietek
    RISE, Swedish ICT, Acreo.
    Ängquist, Lennart
    KTH, Elektrisk energiomvandling.
    Nee, Hans-Peter
    KTH, Elektrisk energiomvandling.
    High-Power Modular Multilevel Converters With SiC JFETs2012In: IEEE transactions on power electronics, ISSN 0885-8993, E-ISSN 1941-0107, Vol. 27, no 1, p. 28-36Article in journal (Refereed)
    Abstract [en]

    This paper studies the possibility of building a modular multilevel converter (M2C) using silicon carbide (SiC) switches. The main focus is on a theoretical investigation of the conduction losses of such a converter and a comparison to a corresponding converter with silicon-insulated gate bipolar transistors. Both SiC BJTs and JFETs are considered and compared in order to choose the most suitable technology. One of the submodules of a down-scaled 3 kVA prototype M2C is replaced with a submodule with SiC JFETs without antiparallel diodes. It is shown that the diode-less operation is possible with the JFETs conducting in the negative direction, leaving the possibility to use the body diode during the switching transients. Experimental waveforms for the SiC submodule verify the feasibility during normal steady-state operation. The loss estimation shows that a 300 MW M2C for high-voltage direct current transmission would potentially have an efficiency of approximately 99.8% if equipped with future 3.3 kV 1.2 kA SiC JFETs.

  • 26.
    Ranstad, Per
    et al.
    Alstom Power, Sweden.
    Giezendanner, Florian
    Alstom Power, Sweden.
    Bakowski, Mietek
    RISE, Swedish ICT, Acreo.
    Lim, Jang-Kwon
    RISE, Swedish ICT, Acreo.
    Tolstoy, Georg
    KTH Royal Institute of Technology, Sweden.
    Ranstad, Anton
    SiC power devices in a soft switching converter including aspects on packaging2014In: ECS Transactions, 2014, no 7, p. 51-59Conference paper (Refereed)
    Abstract [en]

    In many applications of power electronic converters efficiency and size are important figures of merit. Low losses in the power semiconductors as well as high frequency operation are important factors to obtain compact and highly efficient converters. The converters considered in this paper are off-line industrial power supplies (~100 kW) operating at a switching frequency range of 20-40 kHz. Replacing Si power devices by SiC counterparts enables both lower losses and increased switching frequencies. In this paper, experimental results from SiC PiN diodes, (output rectifiers) and SiC MOSFETs, (active switches) are presented.

  • 27. Reshanov, S. A.
    et al.
    Schöner, A.
    Kaplan, W.
    RISE, Swedish ICT, Acreo.
    Zhang, A.
    Lim, Jang-Kwon
    RISE, Swedish ICT, Acreo.
    Bakowskib, M.
    RISE, Swedish ICT, Acreo.
    Full epitaxial trench type buried grid SiC JBS diodes2014In: ECS Transactions, 2014, no 7, p. 289-293Conference paper (Refereed)
    Abstract [en]

    The paper presents the advanced concept of fully epitaxial SiC junction barrier Schottky (JBS) diodes. It combines trench etching with embedded epitaxial re-growth and enables cost-efficient manufacturing. Fabricated devices are rated for 20A / 1200V and have leakage currents below 0.1μA at 1000V blocking voltage.

  • 28.
    Reutersköld Hedlund, Carl
    et al.
    KTH Royal Institute of Technology, Sweden.
    Öberg, Olof
    RISE - Research Institutes of Sweden (2017-2019), ICT, Acreo.
    Lim, Jang-Kwon
    RISE - Research Institutes of Sweden (2017-2019), ICT, Acreo.
    Wang, Qin
    RISE - Research Institutes of Sweden (2017-2019), ICT, Acreo.
    Salter, Michael
    RISE - Research Institutes of Sweden (2017-2019), ICT, Acreo.
    Hammar, Mattias
    KTH Royal Institute of Technology, Sweden.
    Trench-Confined InP-Based Epitaxial Regrowth Using Metal-Organic Vapor-Phase Epitaxy2018In: Physica Status Solidi A, Vol. 215, article id 1700454Article in journal (Refereed)
    Abstract [en]

    In this study, an area-selective metal-organic vapor-phase epitaxy (MOVPE) for trench-confined InP-based epitaxial regrowth in-between arrayed rectangular-shaped device elements is reported. Test structures are fabricated to investigate the influence of MOVPE growth and other processing parameters on regrowth control, doping incorporation, and morphology. For correctly chosen crystallographic mesa orientation and mask geometry, good control of growth selectivity, layer morphology, and doping concentration can be achieved, although with an enhanced and non-constant growth rate. This is discussed in terms of orientation-dependent growth rate and loading effects. In addition, a selective etch and regrowth approach which allows for the processing of field-effect transistors of significance for spatial light modulators with trench-integrated driver electronics is successfully implemented.

  • 29.
    Sadik, Diane
    et al.
    KTH Royal Institute of Technology, Sweden.
    Colmenares, Juan
    KTH Royal Institute of Technology, Sweden.
    Lim, Jang-Kwon
    RISE Research Institutes of Sweden, Digital Systems, Smart Hardware.
    Bakowski, Mietek
    RISE Research Institutes of Sweden, Digital Systems, Smart Hardware.
    Nee, Hans Peter
    KTH Royal Institute of Technology, Sweden.
    Comparison of Thermal Stress during Short-Circuit in Different Types of 1.2 kV SiC Transistors Based on Experiments and Simulations2020In: IEEE Transactions on Industrial Electronics, ISSN 0278-0046, E-ISSN 1557-9948, Vol. 897, p. 595-598Article in journal (Refereed)
    Abstract [en]

    The temperature evolution during a short-circuit fault in the dies of three different Silicon Carbide 1200-V power devices is presented. Transient electro-thermal simulations were performed based on the reconstructed structure of commercially available devices. The simulations reveal the location of the hottest point in each device. The nonisothermal electrical analysis supports the necessity to turn OFF short-circuit events rapidly to protect the immunity of the device after a fault. The analysis also reveal differences in delay required to turn OFF devices depending on their type. A thorough analysis of the temperature rise in the die of the SiC MOSFET device is also presented, where the maximum temperature with regards to different fault cases and circuit characteristics is presented. The impact of the gate resistance, circuit inductance, detection time, drain-source voltage, and gate-source voltage are considered.

  • 30.
    Sadik, Diane Perle
    et al.
    KTH Royal Institute of Technology, Sweden.
    Lim, Jang-Kwon
    RISE - Research Institutes of Sweden (2017-2019), ICT, Acreo.
    Colmenares, Juan
    KTH Royal Institute of Technology, Sweden.
    Bakowski, Mietek
    RISE - Research Institutes of Sweden (2017-2019), ICT, Acreo.
    Nee, Hans Peter
    KTH Royal Institute of Technology, Sweden.
    Comparison of thermal stress during short-circuit in different types of 1.2 kV SiC transistors based on experiments and simulations2016In: Materials Science Forum, 2016, Vol. 897, p. 595-598Conference paper (Refereed)
    Abstract [en]

    The temperature evolution during a short-circuit in the die of three different Silicon Carbide 1200-V power devices is presented. A transient thermal simulation was performed based on the reconstructed structure of commercially available devices. The location of the hottest point in the device is compared. Finally, the analysis supports the necessity to turn off short-circuit events rapidly in order to protect the device after a fault.

  • 31.
    Sadik, Diane-Perle
    et al.
    KTH Royal Institute of Technology, Sweden.
    Heinig, Stefanie
    KTH Royal Institute of Technology, Sweden.
    Jacobs, Keijo
    KTH Royal Institute of Technology, Sweden.
    Johannesson, Daniel
    KTH Royal Institute of Technology, Sweden.
    Lim, Jang-Kwon
    RISE, Swedish ICT, Acreo.
    Nawaz, Muhammad
    ABB Corporate Research, Sweden.
    Dijkhuizen, Frans
    ABB Corporate Research, Sweden.
    Bakowski, Mietek
    RISE, Swedish ICT, Acreo.
    Norrga, Staffan
    KTH Royal Institute of Technology, Sweden.
    Nee, Hans-Peter
    KTH Royal Institute of Technology, Sweden.
    Investigation of the surge current capability of the body diode of SiC MOSFETs for HVDC applications2016In: 2016 18th European Conference on Power Electronics and Applications (EPE'16 ECCE Europe), 2016, article id 7695448Conference paper (Refereed)
    Abstract [en]

    The surge current capability of the body-diode of SiC MOSFETs is experimentally analyzed in order to investigate the possibility of using SiC MOSFETs for HVDC applications. SiC MOSFET discrete devices and modules have been tested with surge currents up to 10 times the rated current and for durations up to 2 ms. Although the presence of stacking faults cannot be excluded, the experiments reveal that the failure may occur due to the latch-up of the parasitic n-p-n transistor located in the SiC MOSFET.

  • 32.
    Schöner, Adolf
    et al.
    Ascatron AB, Sweden.
    Elahipanah, Hossein
    Ascatron AB, Sweden.
    Thierry-Jebali, Nicolas
    Ascatron AB, Sweden.
    Reshanov, Sergey A.
    Ascatron AB, Sweden.
    Kaplan, Wlodek
    Ascatron AB, Sweden.
    Zhang, Andy
    Ascatron AB, Sweden.
    Lim, Jang-Kwon
    RISE, Swedish ICT, Acreo.
    Bakowski, Mietek
    RISE, Swedish ICT, Acreo.
    Progress in buried grid technology for improvements in on-resistance of high voltage SiC devices2016In: ECS Transactions, 2016, Vol. 75, no 12, p. 183-190Conference paper (Refereed)
    Abstract [en]

    Buried grid technology is suggested to protect field sensitive device areas from high electric field in order to improve the high temperature and high voltage performance of SiC devices. More than three orders of magnitude lower leakage currents have been demonstrated at high temperature operation. The drawback is that the total resistance increases due to the introduction of the buried grid leading to higher voltage drop at rated current and higher conduction losses. In this paper, we discuss doping and barrier engineering methods in order to take full advantage of the superior shielding effect of the buried grid technology and at the same time minimize the effect on the current conduction. As example, the design considerations for a 1200 V SiC buried grid JBS diode in terms of epi structure doping as well as buried grid properties is comprehensively investigated to optimize the on-state condition.

  • 33. Tolstoy, G
    et al.
    Peftitsis, D
    Lim, Jang-Kwon
    RISE, Swedish ICT, Acreo.
    Bakowski, Mietek
    RISE, Swedish ICT, Acreo.
    Nee, H-P  
    Circuit modelling of vertical buried-grid SiC JFETs2010In: Materials Science Forum, ISSN 0255-5476, E-ISSN 1662-9752, Vol. 645-648, p. 965-Article in journal (Refereed)
  • 34.
    Wang, Qin
    et al.
    RISE Research Institutes of Sweden, Digital Systems, Smart Hardware.
    Ramvall, Peter
    RISE Research Institutes of Sweden, Digital Systems, Smart Hardware.
    Kumar, Ashutosh
    RISE Research Institutes of Sweden, Digital Systems, Smart Hardware.
    Öberg, Olof
    RISE Research Institutes of Sweden, Digital Systems, Smart Hardware.
    Lim, Jang-Kwon
    RISE Research Institutes of Sweden, Digital Systems, Smart Hardware.
    Krishna Murthy, Hithiksha
    RISE Research Institutes of Sweden, Digital Systems, Smart Hardware.
    Kostov, Konstantin Stoychev
    RISE Research Institutes of Sweden, Digital Systems, Smart Hardware.
    Akbari, Saeed
    RISE Research Institutes of Sweden, Digital Systems, Smart Hardware.
    Bakowski, Mietek
    RISE Research Institutes of Sweden, Digital Systems, Smart Hardware.
    Wide bandgap semiconductor based innovative green technology for digital and industrial applications2023Conference paper (Other academic)
  • 35.
    Zhang, Andy Zhenzhong
    et al.
    RISE, Swedish ICT, Acreo. Ascatron AB, Sweden.
    Reshanov, Sergey A.
    Ascatron AB, Sweden.
    Schöner, Adolf
    Ascatron AB, Sweden.
    Kaplan, Wlodek
    Ascatron AB, Sweden.
    Kwietniewski, Norbert
    Warsaw University of Technology, Poland.
    Lim, Jang-Kwon
    RISE, Swedish ICT, Acreo.
    Bakowski, Mietek
    RISE, Swedish ICT, Acreo.
    Planarization of epitaxial SiC trench structures by plasma ion etching2015In: Materials Science Forum, ISSN 0255-5476, E-ISSN 1662-9752, Vol. 821-823, p. 549-552Article in journal (Refereed)
    Abstract [en]

    In this work, we present a planarization concept for epitaxial SiC trench structures involving reactive ion etching (RIE) and inductive coupled plasma (ICP) dry etching. The general idea is to transfer the flat surface from spun-on BCB/photo-resist layers to deposited silicon dioxide and finally to bulk SiC by applying process conditions with the same etch rate for the different materials. In this way several microns of unwanted material can be removed and planar SiC surfaces are obtained. With this method trench structures filled by epitaxial re-growth can be planarized with smooth surfaces and good homogeneity over the wafer. Cost-efficient device manufacturing can be achieved by using standard semiconductor process equipment. This technology makes it possible to manufacture advanced epitaxial SiC material structures for devices such as trench JBS diodes and double-gate trench JFETs.

  • 36.
    Zhang, Yafan
    et al.
    RISE - Research Institutes of Sweden (2017-2019), ICT, Acreo. Jönköping University, Sweden; KTH Royal Institute of Technology, Sweden.
    Below, Ilja
    Jönköping University, Sweden.
    Bakowski, Mietek
    RISE - Research Institutes of Sweden (2017-2019), ICT, Acreo.
    Lim, Jang-Kwon
    RISE - Research Institutes of Sweden (2017-2019), ICT, Acreo.
    Leisner, Peter
    RISE, SP – Sveriges Tekniska Forskningsinstitut, SP Elektronik.
    Nee, Hans Peter
    KTH Royal Institute of Technology, Sweden.
    Investigation of a finned baseplate material and thickness variation for thermal performance of a SiC power module2014In: 15th international conference on Thermal, Mechanical and Multi-Physics Simulation and Experiments in Microelectronics and Microsystems, IEEE , 2014, , p. 1-8article id 6813817Conference paper (Refereed)
    Abstract [en]

    A simplified transient computational fluid dynamics model of an automotive three-phase double-side liquid cooled silicon carbide power inverter, including pin-fin baseplates, has been developed and qualified for parametric studies. Effective heat transfer coefficients have been extracted from the detailed pin-fin baseplate model for two coolant volume flow rates 2 l/min and 6 l/min, at the coolant temperature 105 °C. The inverter model includes temperature dependent heat losses of SiC transistors and diodes, calculated for two driving cycles. Baseplate materials such as copper, aluminum-silicon carbide metal matrix composite, aluminium alloy 6061 as well as virtual materials have been evaluated in the parametric studies. Thermal conductivity, specific heat and density have been varied as well as thickness of the finned baseplates (1 to 3 mm). A trade-off between temperature of SiC chips and baseplate weight has been investigated by means of Pareto optimization. The main results of the parametric studies include a weak dependence (1 to 3 °C) of the chip temperature on baseplate thickness. Furthermore, switching e.g. between copper and AlSiC results in 5 to 8 °C increase of the chip temperature, at 65 to 70 % baseplate weight reduction.

  • 37. Åstlund, L
    et al.
    Wang, Q
    RISE, Swedish ICT, Acreo.
    Esteve, R
    Almqvist, S
    Rihtnesberg, D
    Reshanov, S
    Zhang, A Z
    Lim, Jang-Kwon
    RISE, Swedish ICT, Acreo.
    Bakowski, Mietek
    RISE, Swedish ICT, Acreo.
    Schöner, A
    Kaplan, W
    4H- 6H-SiC UV photodetectors2012In: Phys. Status Solid, Vol. c9, no 7, p. 1680-2Article in journal (Refereed)
1 - 37 of 37
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