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  • 1.
    Bakowski, Mietek
    et al.
    RISE., Swedish ICT, Acreo.
    Schöner, A
    Petermann, Ingemar
    RISE., Swedish ICT, Acreo.
    Savage, S
    Silicon carbide APD with improved detection sensitivity stability2010Ingår i: Materials Science Forum, ISSN 0255-5476, E-ISSN 1662-9752, Vol. 645-648, s. 1089-Artikel i tidskrift (Refereegranskat)
  • 2. Esteve, R
    et al.
    Schöner, A
    RISE., Swedish ICT, Acreo.
      Reshanov, S A
     Zetterling, C-M  
    Comparative study of thermal oxides post-oxidized deposited oxides on n-type free standing 3C-SiC2010Ingår i: Materials Science Forum, ISSN 0255-5476, E-ISSN 1662-9752, Vol. 645-648, s. 829-32Artikel i tidskrift (Refereegranskat)
  • 3. Gutt, T
    et al.
    Przewlocki, HM
    Bakowski, Mietek
    RISE., Swedish ICT, Acreo.
    A C-V method of slow-switching interface traps identification in silicon carbide MOS structures2010Ingår i: Materials Science Forum, ISSN 0255-5476, E-ISSN 1662-9752, Vol. 645-648, s. 523-Artikel i tidskrift (Refereegranskat)
  • 4.
    Lee, Geon Hee
    et al.
    Kwangwoon University, Republic of Korea.
    Lim, Jang-Kwon
    RISE Research Institutes of Sweden, Digitala system, Smart hårdvara.
    Koo, Sang Mo
    Kwangwoon University, Republic of Korea.
    Bakowski, Mietek
    RISE Research Institutes of Sweden, Digitala system, Smart hårdvara.
    Measurement and Analysis of Body Diode Stress of 3.3 kV Sic-Mosfets with Intrinsic Body Diode and Embedded SBD2023Ingår i: Materials Science Forum, ISSN 0255-5476, E-ISSN 1662-9752, Vol. 1091, s. 55-59Artikel i tidskrift (Refereegranskat)
    Abstract [en]

    SiC MOSFETs display reliability issues related to the quality of SiO2/SiC interface and bulk material due to the presence of near interface traps and point and extended material defects [1]. These material related issues give rise to a degradation of device reliability and ruggedness. One of them are basal plane dislocations (BPDs) introduced in the drift-layer during the epitaxial growth process which causes a s.c. bipolar degradation. Growth and movement of BPDs fueled by recombination energy has a very significant impact on conduction loss and on-resistance degradation. For 3.3 kV voltage capability, the probability of the appearance of BPDs is greater because the drift region is about three times larger compared to 1.2 kV devices [2-3]. We present measurement results and analysis of bipolar degradation in 3.3 kV MOSFETs with conventional body diode and embedded schottky barrier diode (SBD). The measurements were performed applying 50 % and 80 % of rated current with duty cycle 80 %, under total time of 100 hrs at constant case temperature of 54 °C. The 3rd-quadrant performance of both types of MOSFETs in pre-stress conditions was characterized at 25 and 150 °C with different gate biases of -10 V, 0 V, and +17 V. To evaluate the bipolar degradation, the diode conduction characteristics were measured at 25 °C after different stressing times by diode conduction the MOSFET output characteristics were measured at 25 and 54 °C before and after stressing the intrinsic body diode and embedded SBD. No VSD shift was observed in diode conduction characteristics. The results indicate that the MOSFETs were fabricated on appropriate material with a sufficiently low number basal plane dislocation (BPD). The on-state resistance with VGS = +17 V was decreased by temperature due to increased JFET resistance rather than bipolar degradation. On the other hand, the on-state resistance with VGS = +11 V was impacted by the increased temperature and VTH instability.

  • 5.
    Lim, Jang-Kwon
    et al.
    RISE., Swedish ICT, Acreo.
    Bakowski, Mietek
    RISE., Swedish ICT, Acreo.
    Nee, H-P
    Design gate drive considerations for epitaxial 1.2kV buried grid N-on N-off JFETs for operation at 250C2010Ingår i: Materials Science Forum, ISSN 0255-5476, E-ISSN 1662-9752, Vol. 645-648, s. 961-Artikel i tidskrift (Refereegranskat)
  • 6.
    Lim, Jang-Kwon
    et al.
    RISE - Research Institutes of Sweden (2017-2019), ICT, Acreo.
    Tolstoy, G
     Peftitsis, D
    Rabkowski, J
    Bakowski, Mietek
    RISE., Swedish ICT, Acreo.
    Nee, H-P
    KTH Royal Institute of Technology, Sweden.
    Comparison of total losses of 1.2kV SiC JFET BJT in DC-DC converter including gate driver2011Ingår i: Materials Science Forum, ISSN 0255-5476, E-ISSN 1662-9752, Vol. 679-80, s. 649-52Artikel i tidskrift (Refereegranskat)
  • 7.
    Lim, Jang-Kwon
    et al.
    RISE., Swedish ICT, Acreo.
    Åstlund, Ludwig
    Wang, Qin
    RISE., Swedish ICT, Acreo.
    Kaplan, Wlodek
    Reshanov, SA
    Schöner, Adolf
    Bakwoski, Mietek
    Nee, H-P
    A theoretical experimental comparison of 4H- 6H-SiC MSM UV photodetectors2012Ingår i: Materials Science Forum, ISSN 0255-5476, E-ISSN 1662-9752, Vol. 717-720, s. 1207-10Artikel i tidskrift (Refereegranskat)
  • 8.
    Nee, Hans Peter
    et al.
    KTH Royal Institute of Technology, Sweden.
    Rabkowski, Jacek
    KTH Royal Institute of Technology, Sweden.
    Peftitsis, Dimosthenis
    KTH Royal Institute of Technology, Sweden.
    Tolstoy, Georg
    KTH Royal Institute of Technology, Sweden.
    Colmenares, Juan
    KTH Royal Institute of Technology, Sweden.
    Sadik, Diane Perle
    KTH Royal Institute of Technology, Sweden.
    Bakowski, Mietek
    RISE., Swedish ICT, Acreo.
    Lim, Jang-Kwon
    RISE., Swedish ICT, Acreo.
    Antonopoulos, Antonios
    KTH Royal Institute of Technology, Sweden.
    Ängquist, Lennart
    KTH Royal Institute of Technology, Sweden.
    Zdanowski, Mariusz
    Warsaw University of Technology, Poland.
    High-Efficiency Power Conversion Using Silicon Carbide Power Electronics2014Ingår i: Materials Science Forum, ISSN 0255-5476, E-ISSN 1662-9752, Vol. 778-780Artikel i tidskrift (Refereegranskat)
    Abstract [en]

    The message of this paper is that the silicon carbide power transistors of today are good enough to design converters with efficiencies and switching speeds beyond comparison with corresponding technology in silicon. This is the time to act. Only in the highest power range the devices are missing. Another important step towards high powers is to find new solutions for multichip circuit designs that are adapted to the high possible switching speeds of unipolar silicon carbide power transistors.

  • 9. Tolstoy, G
    et al.
    Peftitsis, D
    Lim, Jang-Kwon
    RISE., Swedish ICT, Acreo.
    Bakowski, Mietek
    RISE., Swedish ICT, Acreo.
    Nee, H-P  
    Circuit modelling of vertical buried-grid SiC JFETs2010Ingår i: Materials Science Forum, ISSN 0255-5476, E-ISSN 1662-9752, Vol. 645-648, s. 965-Artikel i tidskrift (Refereegranskat)
  • 10. Weidner, M
    et al.
    Trapaidze, L
      Pensl, G
    Reshanov,  SA
      Schöner, A
    RISE., Swedish ICT, Acreo.
    Itoh,  H
    Ohshima, T
     Kimoto, T
    Deep defects in 3C-SiC generated by H+- He+-implantation or by irradiation with high-energy electrons2010Ingår i: Materials Science Forum, ISSN 0255-5476, E-ISSN 1662-9752, Vol. 645-648, s. 439-442Artikel i tidskrift (Refereegranskat)
  • 11.
    Zhang, Andy Zhenzhong
    et al.
    RISE., Swedish ICT, Acreo. Ascatron AB, Sweden.
    Reshanov, Sergey A.
    Ascatron AB, Sweden.
    Schöner, Adolf
    Ascatron AB, Sweden.
    Kaplan, Wlodek
    Ascatron AB, Sweden.
    Kwietniewski, Norbert
    Warsaw University of Technology, Poland.
    Lim, Jang-Kwon
    RISE., Swedish ICT, Acreo.
    Bakowski, Mietek
    RISE., Swedish ICT, Acreo.
    Planarization of epitaxial SiC trench structures by plasma ion etching2015Ingår i: Materials Science Forum, ISSN 0255-5476, E-ISSN 1662-9752, Vol. 821-823, s. 549-552Artikel i tidskrift (Refereegranskat)
    Abstract [en]

    In this work, we present a planarization concept for epitaxial SiC trench structures involving reactive ion etching (RIE) and inductive coupled plasma (ICP) dry etching. The general idea is to transfer the flat surface from spun-on BCB/photo-resist layers to deposited silicon dioxide and finally to bulk SiC by applying process conditions with the same etch rate for the different materials. In this way several microns of unwanted material can be removed and planar SiC surfaces are obtained. With this method trench structures filled by epitaxial re-growth can be planarized with smooth surfaces and good homogeneity over the wafer. Cost-efficient device manufacturing can be achieved by using standard semiconductor process equipment. This technology makes it possible to manufacture advanced epitaxial SiC material structures for devices such as trench JBS diodes and double-gate trench JFETs.

1 - 11 av 11
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