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Fabrication of a SiC double gate vertical channel jfet and it's application in power electronics
RISE, Swedish ICT, Acreo.
RISE, Swedish ICT, Acreo.ORCID iD: 0000-0002-9512-2689
Denso Corporation, Japan.
Denso Corporation, Japan.
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2012 (English)In: ECS Transactions, 2012, Vol. 50, no 3, p. 45-52Conference paper, Published paper (Refereed)
Abstract [en]

The fabrication process of an innovative epitaxial trench JFET with vertical channel and double gate control is reviewed. Due to the excellent doping and thickness control of the epitaxial regrowth techniques, the sub-micron channel can be tailored for normally-on and -off operation. Due to the vertical channel design the epitaxial trench JFETs have narrow cell pitch for high-density power integration and high saturation current capabilities. The excellent performance of these fabricated and packaged JFET devices is demonstrated with on-wafer measurements and power switching tests. High current conduction tests are performed at room temperature and elevated temperatures of 125°C with switching frequencies of 30 kHz and 200 kHz.

Place, publisher, year, edition, pages
2012. Vol. 50, no 3, p. 45-52
Keywords [en]
Elevated temperature, Epitaxial regrowth, Fabrication process, High saturation current, On-wafer measurements, Power Integrations, Room temperature, Vertical channels, Epitaxial growth, Fabrication, Gallium nitride, Power electronics, Silicon carbide
National Category
Engineering and Technology
Identifiers
URN: urn:nbn:se:ri:diva-51154DOI: 10.1149/05003.0045ecstScopus ID: 2-s2.0-84885781942ISBN: 9781607683513 (print)OAI: oai:DiVA.org:ri-51154DiVA, id: diva2:1514403
Conference
2nd Symposium on Gallium Nitride (GaN) and Silicon Carbide (SiC) Power Technologies - ECS Fall 2012 Meeting, 7 October 2012 through 12 October 2012, Honolulu, HI
Available from: 2021-01-05 Created: 2021-01-05 Last updated: 2024-02-06Bibliographically approved

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Bakowski, Mietek

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CiteExportLink to record
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Citation style
  • apa
  • ieee
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  • nn-NB
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Output format
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  • asciidoc
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