We report on the synthesis of vertical InP nanowire arrays on (001) InP and Si substrates using template-assisted vapour-liquid-solid growth. A thick silicon oxide layer was first deposited on the substrates. The samples were then patterned by electron beam lithography and deep dry etching through the oxide layer down to the substrate surface. Gold seed particles were subsequently deposited in the holes of the pattern by the use of pulse electrodeposition. The subsequent growth of nanowires by the vapour-liquid-solid method was guided towards the [001] direction by the patterned oxide template, and displayed a high growth yield with respect to the array of holes in the template. In order to confirm the versatility and robustness of the process, we have also demonstrated guided growth of InP nanowire p-n junctions and InP/InAs/InP nanowire heterostructures on (001) InP substrates. Our results show a promising route to monolithically integrate III-V nanowire heterostructure devices with commercially viable (001) silicon platforms.