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Register allocation and instruction scheduling in Unison
RISE, Swedish ICT, SICS, Computer Systems Laboratory. KTH Royal Institute of Technology, Sweden.ORCID iD: 0000-0002-2806-7333
RISE, Swedish ICT, SICS, Computer Systems Laboratory.ORCID iD: 0000-0003-3079-8095
KTH Royal Institute of Technology, Sweden.
RISE, Swedish ICT, SICS, Computer Systems Laboratory. KTH Royal Institute of Technology, Sweden.ORCID iD: 0000-0002-6283-7004
2016 (English)In: Proceedings of the 25th International Conference on Compiler Construction, 2016, 6, p. 263-264Conference paper, Published paper (Refereed)
Abstract [en]

This paper describes Unison, a simple, flexible, and potentially optimal software tool that performs register allocation and instruction scheduling in integration using combinatorial optimization. The tool can be used as an alternative or as a complement to traditional approaches, which are fast but complex and suboptimal. Unison is most suitable whenever high-quality code is required and longer compilation times can be tolerated (such as in embedded systems or library releases), or the targeted processors are so irregular that traditional compilers fail to generate satisfactory code.

Place, publisher, year, edition, pages
2016, 6. p. 263-264
National Category
Computer and Information Sciences
Identifiers
URN: urn:nbn:se:ri:diva-24536DOI: 10.1145/2892208.2892237Scopus ID: 2-s2.0-84966560429ISBN: 978-1-4503-4241-4 (print)OAI: oai:DiVA.org:ri-24536DiVA, id: diva2:1043620
Conference
25th International Conference on Compiler Construction (CC 2016), March 17-18, 2016, Barcelona, Spain
Projects
UnisonAvailable from: 2016-10-31 Created: 2016-10-31 Last updated: 2023-05-05Bibliographically approved

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Castaneda Lozano, RobertoCarlsson, MatsSchulte, Christian

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