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Modeling Universal Instruction Selection
RISE, Swedish ICT, SICS, Computer Systems Laboratory.ORCID iD: 0000-0002-2806-7333
RISE, Swedish ICT, SICS, Computer Systems Laboratory.ORCID iD: 0000-0003-3079-8095
RISE, Swedish ICT, SICS, Computer Systems Laboratory.
2015 (English)Conference paper, Published paper (Refereed)
Abstract [en]

Instruction selection implements a program under compilation by selecting processor instructions and has tremendous impact on the performance of the code generated by a compiler. This paper introduces a graph-based universal representation that unifiees data and control flow for both programs and processor instructions. The representation is the essential prerequisite for a constraint model for instruction selection introduced in this paper. The model is demonstrated to be expressive in that it supports many processor features that are out of reach of state-of-the-art approaches, such as advanced branching instructions, multiple register banks, and SIMD instructions. The resulting model can be solved for small to medium size input programs and sophisticated processor instructions and is competitive with LLVM in code quality. Model and representation are significant due to their expressiveness and their potential to be combined with models for other code generation tasks.

Place, publisher, year, edition, pages
2015, 7.
National Category
Computer and Information Science
Identifiers
URN: urn:nbn:se:ri:diva-24436OAI: oai:DiVA.org:ri-24436DiVA: diva2:1043517
Conference
Twenty-first International Conference on Principles and Practice of Constraint Programming
Projects
Unison
Available from: 2016-10-31 Created: 2016-10-31 Last updated: 2017-04-25Bibliographically approved

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