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Constraint-based Register Allocation and Instruction Scheduling
RISE, Swedish ICT, SICS, Computer Systems Laboratory.ORCID iD: 0000-0002-2806-7333
RISE, Swedish ICT, SICS, Computer Systems Laboratory.ORCID iD: 0000-0003-3079-8095
RISE, Swedish ICT, SICS, Computer Systems Laboratory.ORCID iD: 0000-0002-2637-2991
RISE, Swedish ICT, SICS, Computer Systems Laboratory.ORCID iD: 0000-0002-6283-7004
2012 (English)Conference paper, Published paper (Refereed)
Abstract [en]

This paper introduces a constraint model and solving techniques for code generation in a compiler back-end. It contributes a new model for global register allocation that combines several advanced aspects: multiple register banks (subsuming spilling to memory), coalescing, and packing. The model is extended to include instruction scheduling and bundling. The paper introduces a decomposition scheme exploiting the underlying program structure and exhibiting robust behavior for functions with thousands of instructions. Evaluation shows that code quality is on par with LLVM, a state-of-the-art compiler infrastructure. The paper makes important contributions to the applicability of constraint programming as well as compiler construction: essential concepts are unified in a high-level model that can be solved by readily available modern solvers. This is a significant step towards basing code generation entirely on a high-level model and by this facilitates the construction of correct, simple, flexible, robust, and high-quality code generators.

Place, publisher, year, edition, pages
2012, 6. p. 750-766
National Category
Computer and Information Sciences
Identifiers
URN: urn:nbn:se:ri:diva-24215OAI: oai:DiVA.org:ri-24215DiVA, id: diva2:1043295
Conference
Eighteenth International Conference on Principles and Practice of Constraint Programming
Projects
UnisonAvailable from: 2016-10-31 Created: 2016-10-31 Last updated: 2023-05-16Bibliographically approved

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Castaneda Lozano, RobertoCarlsson, MatsDrejhammar, FrejSchulte, Christian

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