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A Compact Intermediate Format for SimICS
RISE - Research Institutes of Sweden, ICT, SICS.
1994 (English)Report (Other academic)
Abstract [en]

Instruction set architecture (ISA) simulators are an increasingly popular class of tools for both research and commercial purposes. Common applications include trace generation, program development, and compatibility support. A major concern with ISA simulators is performance and memory overhead. A common technique for achieving good performance is to use threaded code, which involves translating the target object code to an intermediate format which is subsequently interpreted. We describe such an internal format, which we call the 64-bit format, that is compact and meets a range of requirements in terms of flexibility and simplicity. We show how a simulator using this format can be implemented efficiently by taking advantage of extensions to the C language supported by the GNU C compilers. We have used the format to write the core interpreter in SimICS, a system level multiprocessor simulator that supports the Motorola 88110 and the SPARC V8 instruction sets.

Place, publisher, year, edition, pages
Swedish Institute of Computer Science , 1994, 1.
Series
SICS Research Report, ISSN 0283-3638 ; R94:17
Keywords [en]
Intermediate Representation, Interpreter, Simulator, InstructionSet, Architecture, SPARC, m88110, C, GCC
National Category
Computer and Information Sciences
Identifiers
URN: urn:nbn:se:ri:diva-21388OAI: oai:DiVA.org:ri-21388DiVA, id: diva2:1041424
Available from: 2016-10-31 Created: 2016-10-31 Last updated: 2018-02-02Bibliographically approved

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CiteExportLink to record
Permanent link

Direct link
Cite
Citation style
  • apa
  • harvard1
  • ieee
  • modern-language-association-8th-edition
  • vancouver
  • Other style
More styles
Language
  • de-DE
  • en-GB
  • en-US
  • fi-FI
  • nn-NO
  • nn-NB
  • sv-SE
  • Other locale
More languages
Output format
  • html
  • text
  • asciidoc
  • rtf
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