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Some Efficient Techniques for Simulating Memory
RISE - Research Institutes of Sweden, ICT, SICS.
RISE - Research Institutes of Sweden, ICT, SICS.
1994 (English)Report (Other academic)
Abstract [en]

We describe novel techniques used for efficient simulation of memory in SimICS, an instruction level simulator developed at SICS. The design has focused on efficiently supporting the simulation of multiprocessors, analyzing complex memory hierarchies and running large binaries with a mixture of system-level and user-level code. A software caching mechanism (the Simulator Translation Cache, STC) improves the performance of interpreted memory operations by reducing the number of calls to complex memory simulation code. A lazy memory allocation scheme reduces the size of the simulator process. A well-defined internal interface to generic memory simulation simplifies user extensions. Leveraging on a flexible interpreter based on threaded code allows runtime selection of statistics gathering, memory profiling, and cache simulation with low overhead. The result is a memory simulation that supports a range of features for use in computer architecture research, program profiling, and debugging. (NOTE: A later version was published in the 28th Annual Simulation Symposium)

Place, publisher, year, edition, pages
Swedish Institute of Computer Science , 1994, 1.
Series
SICS Research Report, ISSN 0283-3638 ; R94:16
Keywords [en]
Interpreter, Simulator, Multiprocessor, SimICS, Memory Simulation, Memory Hierarchy, Cache Simulation
National Category
Computer and Information Sciences
Identifiers
URN: urn:nbn:se:ri:diva-21387OAI: oai:DiVA.org:ri-21387DiVA, id: diva2:1041423
Available from: 2016-10-31 Created: 2016-10-31 Last updated: 2018-02-02Bibliographically approved

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CiteExportLink to record
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  • apa
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