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DDM - a cache-only memory architecture
RISE, Swedish ICT, SICS.
RISE, Swedish ICT, SICS, Computer Systems Laboratory.ORCID iD: 0000-0002-6718-0144
RISE, Swedish ICT, SICS.
1991 (English)Report (Other academic)
Abstract [en]

The long latencies introduced by remote accesses in a large multiprocessor can be hidden by caching. Caching also decreases the network load. We introduce a new class of architectures called Cache Only Memory Archi-tectures (COMA). These architectures provide the programming paradigm of the shared-memory architectures, but have no physically shared memory; instead, the caches attached to the processors containallthe memory in the system, and their size is therefore large. A datum is allowed to be in any or many of the caches, and will automatically be moved to where it is needed by a cache-coherence protocol,which also ensures that the last copy of a datum is never lost. The location of a datum in the machine is completely decoupled from its address. We also introduce one example of COMA: the Data Diffusion Machine (DDM), and its simulated performance for large applications. The DDM is based on a hierarchical network structure, with processor/memory pairs at its tips. Remote accesses generally cause only a limited amount of traffic over a limited part of the machine.

Place, publisher, year, edition, pages
Swedish Institute of Computer Science , 1991, 1. , p. 10
Series
SICS Research Report, ISSN 0283-3638 ; R91:19
Keywords [en]
Multiprocesor, COMA, hierarchical architeture, hierarchical buses, multilevel cache, shared memory, split-transaction bus, cache coherence, cache-only memory architecture
National Category
Computer and Information Sciences
Identifiers
URN: urn:nbn:se:ri:diva-21359OAI: oai:DiVA.org:ri-21359DiVA, id: diva2:1041395
Available from: 2016-10-31 Created: 2016-10-31 Last updated: 2018-01-14Bibliographically approved

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CiteExportLink to record
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Citation style
  • apa
  • harvard1
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  • en-GB
  • en-US
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Output format
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