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Feasibility study of FPGA-based equalizer for 112-Gbit/s optical fiber receivers
Chalmers University of Technology, Sweden.
Chalmers University of Technology, Sweden.
RISE, Swedish ICT, Acreo.ORCID iD: 0000-0002-8160-4484
RISE, Swedish ICT, Acreo.ORCID iD: 0000-0001-5905-0530
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2012 (English)In: ISCAS 2012 - 2012 IEEE International Symposium on Circuits and Systems, 2012, p. 3234-3237, article id 6272013Conference paper, Published paper (Refereed)
Abstract [en]

With ever increasing demands on spectral efficiency, complex modulation schemes are being introduced in fiber communication. However, these schemes are challenging to implement as they drastically increase the computational burden at the fiber receiver's end. We perform a feasibility study of implementing a 16-QAM112-Gbit/s decision directed equalizer on a state-of-the-art FPGA platform. An FPGA offers the reconfigurability needed to allow for modulation scheme updates, however, its clock rate is limited. For this purpose, we introduce a new phase correction technique to significantly relax the delay requirement on the critical phase-recovery feedback loop.

Place, publisher, year, edition, pages
2012. p. 3234-3237, article id 6272013
Keywords [en]
Clock rate, Complex modulation, Computational burden, Decision-directed, Feasibility studies, Feed-back loop, In-fiber, Modulation schemes, Phase corrections, Reconfigurability, Spectral efficiencies, Field programmable gate arrays (FPGA), Modulation, Optical fibers, Planning, Spectrum analyzers, Equalizers
National Category
Engineering and Technology
Identifiers
URN: urn:nbn:se:ri:diva-51771DOI: 10.1109/ISCAS.2012.6272013Scopus ID: 2-s2.0-84866596205OAI: oai:DiVA.org:ri-51771DiVA, id: diva2:1516951
Conference
2012 IEEE International Symposium on Circuits and Systems, ISCAS 2012, 20 May 2012 through 23 May 2012, Seoul
Available from: 2021-01-13 Created: 2021-01-13 Last updated: 2021-06-14Bibliographically approved

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Mårtensson, JonasForzati, Marco

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