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Combinatorial Spill Code Optimization and Ultimate Coalescing
RISE., Swedish ICT, SICS, Computer Systems Laboratory.ORCID-id: 0000-0002-2806-7333
RISE., Swedish ICT, SICS, Computer Systems Laboratory.ORCID-id: 0000-0003-3079-8095
KTH Royal Institute of Technology, Sweden.
RISE., Swedish ICT, SICS, Computer Systems Laboratory.ORCID-id: 0000-0002-6283-7004
2014 (engelsk)Konferansepaper, Publicerat paper (Fagfellevurdert)
Abstract [en]

This paper presents a novel combinatorial model that integrates global register allocation based on ultimate coalescing, spill code optimization, register packing, and multiple register banks with instruction scheduling (including VLIW). The model exploits alternative temporaries that hold the same value as a new concept for ultimate coalescing and spill code optimization. The paper presents Unison as a code generator based on the model and advanced solving techniques using constraint programming. Thorough experiments using MediaBench and a processor (Hexagon) that are typical for embedded systems demonstrate that Unison: is robust and scalable; generates faster code than LLVM (up to 41% with a mean improvement of 7%); possibly generates optimal code (for 29% of the experiments); effortlessly supports different optimization criteria (code size on par with LLVM). Unison is significant as it addresses the same aspects as traditional code generation algorithms, yet is based on a simple integrated model and robustly can generate optimal code.

sted, utgiver, år, opplag, sider
2014, 5. s. 23-32
HSV kategori
Identifikatorer
URN: urn:nbn:se:ri:diva-24161DOI: 10.1145/2597809.2597815Scopus ID: 2-s2.0-84907032397OAI: oai:DiVA.org:ri-24161DiVA, id: diva2:1043240
Konferanse
Fourteenth ACM SIGPLAN/SIGBED Conference on Languages, Compilers and Tools for Embedded Systems
Prosjekter
UnisonTilgjengelig fra: 2016-10-31 Laget: 2016-10-31 Sist oppdatert: 2020-01-24bibliografisk kontrollert

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Totalt: 4 treff
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