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Publications (10 of 37) Show all publications
Lee, G. H., Lim, J.-K., Koo, S. M. & Bakowski, M. (2023). Measurement and Analysis of Body Diode Stress of 3.3 kV Sic-Mosfets with Intrinsic Body Diode and Embedded SBD. Materials Science Forum, 1091, 55-59
Open this publication in new window or tab >>Measurement and Analysis of Body Diode Stress of 3.3 kV Sic-Mosfets with Intrinsic Body Diode and Embedded SBD
2023 (English)In: Materials Science Forum, ISSN 0255-5476, E-ISSN 1662-9752, Vol. 1091, p. 55-59Article in journal (Refereed) Published
Abstract [en]

SiC MOSFETs display reliability issues related to the quality of SiO2/SiC interface and bulk material due to the presence of near interface traps and point and extended material defects [1]. These material related issues give rise to a degradation of device reliability and ruggedness. One of them are basal plane dislocations (BPDs) introduced in the drift-layer during the epitaxial growth process which causes a s.c. bipolar degradation. Growth and movement of BPDs fueled by recombination energy has a very significant impact on conduction loss and on-resistance degradation. For 3.3 kV voltage capability, the probability of the appearance of BPDs is greater because the drift region is about three times larger compared to 1.2 kV devices [2-3]. We present measurement results and analysis of bipolar degradation in 3.3 kV MOSFETs with conventional body diode and embedded schottky barrier diode (SBD). The measurements were performed applying 50 % and 80 % of rated current with duty cycle 80 %, under total time of 100 hrs at constant case temperature of 54 °C. The 3rd-quadrant performance of both types of MOSFETs in pre-stress conditions was characterized at 25 and 150 °C with different gate biases of -10 V, 0 V, and +17 V. To evaluate the bipolar degradation, the diode conduction characteristics were measured at 25 °C after different stressing times by diode conduction the MOSFET output characteristics were measured at 25 and 54 °C before and after stressing the intrinsic body diode and embedded SBD. No VSD shift was observed in diode conduction characteristics. The results indicate that the MOSFETs were fabricated on appropriate material with a sufficiently low number basal plane dislocation (BPD). The on-state resistance with VGS = +17 V was decreased by temperature due to increased JFET resistance rather than bipolar degradation. On the other hand, the on-state resistance with VGS = +11 V was impacted by the increased temperature and VTH instability.

National Category
Computer Sciences
Identifiers
urn:nbn:se:ri:diva-66645 (URN)10.4028/p-nnor4r (DOI)
Note

This paper is supported by the MOTIE (Ministry of Trade, Industry, and Energy, Korea) under the Fostering Global Talents for Innovative Growth Program (P0017308) supervised by the Korea Institute for Advancement of Technology (KIAT), RISE Research Institutes of Sweden AB visiting scholar program, and European Union’s Horizon 2020 research and innovation programme under grant agreement (Recet4Rail, 101015423)

Available from: 2023-09-05 Created: 2023-09-05 Last updated: 2024-04-05Bibliographically approved
Wang, Q., Ramvall, P., Kumar, A., Öberg, O., Lim, J.-K., Krishna Murthy, H., . . . Bakowski, M. (2023). Wide bandgap semiconductor based innovative green technology for digital and industrial applications. In: : . Paper presented at 244th Electrochemical Society Meeting October 8-12, 2023 in Gothenburg Sweden..
Open this publication in new window or tab >>Wide bandgap semiconductor based innovative green technology for digital and industrial applications
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2023 (English)Conference paper, Oral presentation with published abstract (Other academic)
National Category
Computer and Information Sciences
Identifiers
urn:nbn:se:ri:diva-65524 (URN)
Conference
244th Electrochemical Society Meeting October 8-12, 2023 in Gothenburg Sweden.
Available from: 2023-06-22 Created: 2023-06-22 Last updated: 2024-05-22Bibliographically approved
Akbari, S., Kostov, K. S., Brinkfeldt, K., Adolfsson, E., Lim, J.-K., Andersson, D., . . . Salter, M. (2022). Ceramic Additive Manufacturing Potential for Power Electronics Packaging. IEEE Transactions on Components, Packaging, and Manufacturing Technology, 12(11), 1857-1866
Open this publication in new window or tab >>Ceramic Additive Manufacturing Potential for Power Electronics Packaging
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2022 (English)In: IEEE Transactions on Components, Packaging, and Manufacturing Technology, ISSN 2156-3950, E-ISSN 2156-3985, Vol. 12, no 11, p. 1857-1866Article in journal (Refereed) Published
Abstract [en]

Compared with silicon-based power devices, wide band gap (WBG) semiconductor devices operate at significantly higher power densities required in applications such as electric vehicles and more electric airplanes. This necessitates development of power electronics packages with enhanced thermal characteristics that fulfil the electrical insulation requirements. The present research investigates the feasibility of using ceramic additive manufacturing (AM), also known as three-dimensional (3D) printing, to address thermal and electrical requirements in packaging gallium nitride (GaN) based high-electron-mobility transistors (HEMTs). The goal is to exploit design freedom and manufacturing flexibility provided by ceramic AM to fabricate power device packages with a lower junction-to-ambient thermal resistance (<italic>R</italic>&#x03B8;JA). Ceramic AM also enables incorporation of intricate 3D features into the package structure in order to control the isolation distance between the package source and drain contact pads. Moreover, AM allows to fabricate different parts of the packaging assembly as a single structure to avoid high thermal resistance interfaces. For example, the ceramic package and the ceramic heatsink can be printed as a single part without any bonding layer. Thermal simulations under different thermal loading and cooling conditions show the improvement of thermal performance of the package fabricated by ceramic AM. If assisted by an efficient cooling strategy, the proposed package has the potential to reduce <italic>R</italic>&#x03B8;JA by up to 48%. The results of the preliminary efforts to fabricate the ceramic package by AM are presented, and the challenges that have to be overcome for further development of this manufacturing method are recognized and discussed. 

Place, publisher, year, edition, pages
Institute of Electrical and Electronics Engineers Inc., 2022
Keywords
Ceramic additive manufacturing, GaN HEMTs, isolation distance, power electronics packaging, thermal resistance, wide band gap semiconductors, 3D printers, Ceramic materials, Chip scale packages, Energy gap, Fabrication, Gallium nitride, High electron mobility transistors, III-V semiconductors, Industrial research, Thermal insulation, Ceramic additives, Ceramic package, Gallium nitride high-electron-mobility transistor, High electron-mobility transistors, Power devices, Silicon-based, Wide-band-gap semiconductor
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:ri:diva-62617 (URN)10.1109/TCPMT.2022.3224921 (DOI)2-s2.0-85144078339 (Scopus ID)
Note

This work supported by the Electronic Components and Systems for European Leadership (ECSEL) Joint Undertaking (JU) through the UltimateGaN Project and the European Union’s Horizon 2020 Research and Innovation Programunder Grant 826392.

Available from: 2023-01-20 Created: 2023-01-20 Last updated: 2024-04-05Bibliographically approved
Sadik, D., Colmenares, J., Lim, J.-K., Bakowski, M. & Nee, H. P. (2020). Comparison of Thermal Stress during Short-Circuit in Different Types of 1.2 kV SiC Transistors Based on Experiments and Simulations. IEEE Transactions on Industrial Electronics, 897, 595-598
Open this publication in new window or tab >>Comparison of Thermal Stress during Short-Circuit in Different Types of 1.2 kV SiC Transistors Based on Experiments and Simulations
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2020 (English)In: IEEE Transactions on Industrial Electronics, ISSN 0278-0046, E-ISSN 1557-9948, Vol. 897, p. 595-598Article in journal (Refereed) Published
Abstract [en]

The temperature evolution during a short-circuit fault in the dies of three different Silicon Carbide 1200-V power devices is presented. Transient electro-thermal simulations were performed based on the reconstructed structure of commercially available devices. The simulations reveal the location of the hottest point in each device. The nonisothermal electrical analysis supports the necessity to turn OFF short-circuit events rapidly to protect the immunity of the device after a fault. The analysis also reveal differences in delay required to turn OFF devices depending on their type. A thorough analysis of the temperature rise in the die of the SiC MOSFET device is also presented, where the maximum temperature with regards to different fault cases and circuit characteristics is presented. The impact of the gate resistance, circuit inductance, detection time, drain-source voltage, and gate-source voltage are considered.

Keywords
Silicon carbide, MOSFET, JFETs, Circuit faults, Temperature, Integrated circuit modeling, Performance evaluation, Silicon Carbide (SiC), JFET, BJT, Reliability, Device Simuation, Short-circuit currents, Failure Analysis
National Category
Natural Sciences
Identifiers
urn:nbn:se:ri:diva-44538 (URN)10.1109/TIE.2020.2972442 (DOI)2-s2.0-85020002693 (Scopus ID)
Available from: 2020-03-17 Created: 2020-03-17 Last updated: 2024-04-08Bibliographically approved
Lang, J., Lim, J.-K., Hellén, J., Nilsson, T. M. .., Schödt, B., Poder, R., . . . Leisner, P. (2018). Reliability Study of GaN-onSiC HEMT RF Power Amplifiers. Advances in Technology Innovation, 3(4), 157-165
Open this publication in new window or tab >>Reliability Study of GaN-onSiC HEMT RF Power Amplifiers
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2018 (English)In: Advances in Technology Innovation, Vol. 3, no 4, p. 157-165Article in journal (Refereed) Published
Abstract [en]

The RF power amplifier demonstrators containing each one GaN-on-SiC, HEMT, CHZ015A-QEG, from UMSin SMD quad-flat no-leads package (QFN) were subjected to thermal cycles (TC) and power cycles (PC) andevaluated electrically, thermally and structurally. Two types of solders, Sn63Pb36Ag2 and lead-free SnAgCu(SAC305), and two types of TIM materials, NanoTIM and TgonTM 805, for PCB attachment to the liquid cold platewere tested for thermo-mechanical reliability. Changes in the electrical performance of the devices, namely thereduction of the current saturation value, threshold voltage shift, increase of the leakage current and degradation ofthe HF performance were observed as a result of an accumulated current stress during PC. No significant changes inthe investigated solder or TIM materials were observed.

Keywords
GaN-on SiC, HEMT, RF power amplifier, thermo-mechanical and electrical reliability
National Category
Telecommunications
Identifiers
urn:nbn:se:ri:diva-36943 (URN)
Available from: 2018-12-28 Created: 2018-12-28 Last updated: 2024-04-05Bibliographically approved
Reutersköld Hedlund, C., Öberg, O., Lim, J.-K., Wang, Q., Salter, M. & Hammar, M. (2018). Trench-Confined InP-Based Epitaxial Regrowth Using Metal-Organic Vapor-Phase Epitaxy. Physica Status Solidi A, 215, Article ID 1700454.
Open this publication in new window or tab >>Trench-Confined InP-Based Epitaxial Regrowth Using Metal-Organic Vapor-Phase Epitaxy
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2018 (English)In: Physica Status Solidi A, Vol. 215, article id 1700454Article in journal (Refereed) Published
Abstract [en]

In this study, an area-selective metal-organic vapor-phase epitaxy (MOVPE) for trench-confined InP-based epitaxial regrowth in-between arrayed rectangular-shaped device elements is reported. Test structures are fabricated to investigate the influence of MOVPE growth and other processing parameters on regrowth control, doping incorporation, and morphology. For correctly chosen crystallographic mesa orientation and mask geometry, good control of growth selectivity, layer morphology, and doping concentration can be achieved, although with an enhanced and non-constant growth rate. This is discussed in terms of orientation-dependent growth rate and loading effects. In addition, a selective etch and regrowth approach which allows for the processing of field-effect transistors of significance for spatial light modulators with trench-integrated driver electronics is successfully implemented.

Keywords
InP, metal-organic vapor-phase epitaxy, patterned substrate epitaxy, spatial light modulator
National Category
Computer and Information Sciences
Identifiers
urn:nbn:se:ri:diva-33115 (URN)10.1002/pssa.201700454 (DOI)2-s2.0-85040201992 (Scopus ID)
Available from: 2018-01-17 Created: 2018-01-17 Last updated: 2024-05-22Bibliographically approved
Elahipanah, H., Thierry-Jebali, N., Reshanov, S. A., Kaplan, W., Zhang, A., Lim, J.-K., . . . Schöner, A. (2017). Design optimization of a high temperature 1.2 kV 4H-SiC buried grid JBS rectifier. In: 11th European Conference on Silicon Carbide and Related Materials, ECSCRM 2016: . Paper presented at 25 September 2016 through 29 September 2016 (pp. 455-458).
Open this publication in new window or tab >>Design optimization of a high temperature 1.2 kV 4H-SiC buried grid JBS rectifier
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2017 (English)In: 11th European Conference on Silicon Carbide and Related Materials, ECSCRM 2016, 2017, p. 455-458Conference paper, Published paper (Refereed)
Abstract [en]

1.2 kV SiC buried grid junction barrier Schottky (BG-JBS) diodes are demonstrated. The design considerations for high temperature applications are investigated. The design is optimized in terms of doping concentration and thickness of the epilayers, as well as grid size and spacing dimensions, in order to obtain low on-resistance and reasonable leakage current even at high temperatures. The device behavior at temperatures ranging from 25 to 250ºC is analyzed and measured on wafer level. The forward voltage drop of 1.1 V at 100 A/cm2 and 3.8 V at 1000 A/cm2 is measured, respectively. At reverse voltage of 1 kV, a leakage current density below 0.1 μA/cm2 and below 0.1 mA/cm2 is measured at 25 and 250ºC, respectively. This proves the effective shielding effect of the BG-JBS design and provides benefits in high voltage applications, particularly for high temperature operation.

Keywords
Buried grid, High temperature, High voltage, Junction barrier Schottky (JBS), Silicon carbide (SiC), High temperature applications, High temperature operations, Rectifying circuits, Schottky barrier diodes, Semiconductor junctions, Silicon, Silicon carbide, Silicon wafers, Junction Barrier Schottky, Silicon carbides (SiC), Power semiconductor diodes
National Category
Natural Sciences
Identifiers
urn:nbn:se:ri:diva-31120 (URN)10.4028/www.scientific.net/MSF.897.455 (DOI)2-s2.0-85020051562 (Scopus ID)9783035710434 (ISBN)
Conference
25 September 2016 through 29 September 2016
Available from: 2017-08-28 Created: 2017-08-28 Last updated: 2024-04-05Bibliographically approved
Sadik, D. P., Lim, J.-K., Colmenares, J., Bakowski, M. & Nee, H. P. (2016). Comparison of thermal stress during short-circuit in different types of 1.2 kV SiC transistors based on experiments and simulations. In: Materials Science Forum: . Paper presented at 11th European Conference on Silicon Carbide and Related Materials (ECSCRM 2016), September 25-29, 2016, Halkidiki, Greece (pp. 595-598). , 897
Open this publication in new window or tab >>Comparison of thermal stress during short-circuit in different types of 1.2 kV SiC transistors based on experiments and simulations
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2016 (English)In: Materials Science Forum, 2016, Vol. 897, p. 595-598Conference paper, Published paper (Refereed)
Abstract [en]

The temperature evolution during a short-circuit in the die of three different Silicon Carbide 1200-V power devices is presented. A transient thermal simulation was performed based on the reconstructed structure of commercially available devices. The location of the hottest point in the device is compared. Finally, the analysis supports the necessity to turn off short-circuit events rapidly in order to protect the device after a fault.

Keywords
Bipolar junction transistor (BJT), Failure analysis, Junction field-effect transistor (JFET), Power MOSFET, Semiconductor device reliability, Short-circuit current, Silicon carbide (SiC), Widebandgap semiconductors
National Category
Computer and Information Sciences
Identifiers
urn:nbn:se:ri:diva-31105 (URN)10.4028/www.scientific.net/MSF.897.595 (DOI)2-s2.0-85020002693 (Scopus ID)9783035710434 (ISBN)
Conference
11th European Conference on Silicon Carbide and Related Materials (ECSCRM 2016), September 25-29, 2016, Halkidiki, Greece
Available from: 2017-08-28 Created: 2017-08-28 Last updated: 2024-04-08Bibliographically approved
Kostov, K. S., Lim, J.-K., Zhang, Y. F. & Bakowski, M. (2016). Impact of package parasitics on switching performance. In: Materials Science Forum: . Paper presented at 16th International Conference on Silicon Carbide and Related Materials (ICSCRM 2015), October 4-9, 2015, Sicily, Italy (pp. 1057-1060). , 858
Open this publication in new window or tab >>Impact of package parasitics on switching performance
2016 (English)In: Materials Science Forum, 2016, Vol. 858, p. 1057-1060Conference paper, Published paper (Refereed)
Abstract [en]

The package parasitics are a serious obstacle to the high-speed switching, which is necessary in order to reduce the switching power losses or reduce the size of power converters. In order to design new packages suitable for Silicon Carbide (SiC) power transistors, it is necessary to extract the parasitics of different packages and be able to predict the switching performance of the power devices placed in these packages. This paper presents two ways of simulating the switching performance in a half-bridge power module with SiC MOSFETs. The results show that the parasitic inductances in the power module slow down the switching, lead to poor current sharing, and together with the parasitic capacitances lead to oscillations. These negative effects can cause failures, increased losses, and electromagnetic compatibility issues.

Keywords
Module, MOSFET, Parasitic inductance, Parasitics, Silicon Carbide (SiC), Switching, Capacitance, Electric power systems, Inductance, MOSFET devices, Power semiconductor devices, Silicon, Silicon carbide, MOS-FET, Parasitic inductances, Silicon carbides (SiC)
National Category
Computer and Information Sciences
Identifiers
urn:nbn:se:ri:diva-32592 (URN)10.4028/www.scientific.net/MSF.858.1057 (DOI)2-s2.0-84971539866 (Scopus ID)9783035710427 (ISBN)
Conference
16th International Conference on Silicon Carbide and Related Materials (ICSCRM 2015), October 4-9, 2015, Sicily, Italy
Available from: 2017-11-10 Created: 2017-11-10 Last updated: 2024-04-05Bibliographically approved
Sadik, D.-P., Heinig, S., Jacobs, K., Johannesson, D., Lim, J.-K., Nawaz, M., . . . Nee, H.-P. (2016). Investigation of the surge current capability of the body diode of SiC MOSFETs for HVDC applications. In: 2016 18th European Conference on Power Electronics and Applications (EPE'16 ECCE Europe): . Paper presented at 18th European Conference on Power Electronics and Applications (EPE 2016 ECCE Europe), September 5-9, 2016, Karlsruhe, Germany. , Article ID 7695448.
Open this publication in new window or tab >>Investigation of the surge current capability of the body diode of SiC MOSFETs for HVDC applications
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2016 (English)In: 2016 18th European Conference on Power Electronics and Applications (EPE'16 ECCE Europe), 2016, article id 7695448Conference paper, Published paper (Refereed)
Abstract [en]

The surge current capability of the body-diode of SiC MOSFETs is experimentally analyzed in order to investigate the possibility of using SiC MOSFETs for HVDC applications. SiC MOSFET discrete devices and modules have been tested with surge currents up to 10 times the rated current and for durations up to 2 ms. Although the presence of stacking faults cannot be excluded, the experiments reveal that the failure may occur due to the latch-up of the parasitic n-p-n transistor located in the SiC MOSFET.

Keywords
Diode, Faults, MOSFET, Reliability, Silicon Carbide (SiC), Voltage Source Converter (VSC), DC power transmission, Diodes, Faulting, HVDC power transmission, Power electronics, Silicon carbide, Stacking faults, Discrete devices, MOS-FET, N-p-n transistors, Rated currents, SiC MOSFETs, Silicon carbides (SiC), Surge current, Voltage source converters, MOSFET devices
National Category
Computer and Information Sciences
Identifiers
urn:nbn:se:ri:diva-32565 (URN)10.1109/EPE.2016.7695448 (DOI)2-s2.0-84996938039 (Scopus ID)978-9-0758-1524-5 (ISBN)
Conference
18th European Conference on Power Electronics and Applications (EPE 2016 ECCE Europe), September 5-9, 2016, Karlsruhe, Germany
Available from: 2017-11-10 Created: 2017-11-10 Last updated: 2024-04-08Bibliographically approved
Organisations
Identifiers
ORCID iD: ORCID iD iconorcid.org/0000-0002-9850-9440

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