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Lee, G. H., Lim, J.-K., Koo, S. M. & Bakowski, M. (2023). Measurement and Analysis of Body Diode Stress of 3.3 kV Sic-Mosfets with Intrinsic Body Diode and Embedded SBD. Materials Science Forum, 1091, 55-59
Open this publication in new window or tab >>Measurement and Analysis of Body Diode Stress of 3.3 kV Sic-Mosfets with Intrinsic Body Diode and Embedded SBD
2023 (English)In: Materials Science Forum, ISSN 0255-5476, E-ISSN 1662-9752, Vol. 1091, p. 55-59Article in journal (Refereed) Published
Abstract [en]

SiC MOSFETs display reliability issues related to the quality of SiO2/SiC interface and bulk material due to the presence of near interface traps and point and extended material defects [1]. These material related issues give rise to a degradation of device reliability and ruggedness. One of them are basal plane dislocations (BPDs) introduced in the drift-layer during the epitaxial growth process which causes a s.c. bipolar degradation. Growth and movement of BPDs fueled by recombination energy has a very significant impact on conduction loss and on-resistance degradation. For 3.3 kV voltage capability, the probability of the appearance of BPDs is greater because the drift region is about three times larger compared to 1.2 kV devices [2-3]. We present measurement results and analysis of bipolar degradation in 3.3 kV MOSFETs with conventional body diode and embedded schottky barrier diode (SBD). The measurements were performed applying 50 % and 80 % of rated current with duty cycle 80 %, under total time of 100 hrs at constant case temperature of 54 °C. The 3rd-quadrant performance of both types of MOSFETs in pre-stress conditions was characterized at 25 and 150 °C with different gate biases of -10 V, 0 V, and +17 V. To evaluate the bipolar degradation, the diode conduction characteristics were measured at 25 °C after different stressing times by diode conduction the MOSFET output characteristics were measured at 25 and 54 °C before and after stressing the intrinsic body diode and embedded SBD. No VSD shift was observed in diode conduction characteristics. The results indicate that the MOSFETs were fabricated on appropriate material with a sufficiently low number basal plane dislocation (BPD). The on-state resistance with VGS = +17 V was decreased by temperature due to increased JFET resistance rather than bipolar degradation. On the other hand, the on-state resistance with VGS = +11 V was impacted by the increased temperature and VTH instability.

National Category
Computer Sciences
Identifiers
urn:nbn:se:ri:diva-66645 (URN)10.4028/p-nnor4r (DOI)
Note

This paper is supported by the MOTIE (Ministry of Trade, Industry, and Energy, Korea) under the Fostering Global Talents for Innovative Growth Program (P0017308) supervised by the Korea Institute for Advancement of Technology (KIAT), RISE Research Institutes of Sweden AB visiting scholar program, and European Union’s Horizon 2020 research and innovation programme under grant agreement (Recet4Rail, 101015423)

Available from: 2023-09-05 Created: 2023-09-05 Last updated: 2024-04-05Bibliographically approved
Yuan, Z., Schöner, A., Reshanov, S., Kaplan, W., Bakowski, M. & Hallen, A. (2023). Tailoring the Charge Carrier Lifetime Distribution of 10 kV SiC PiN Diodes by Physical Simulations. Key Engineering Materials, 946, 119-124
Open this publication in new window or tab >>Tailoring the Charge Carrier Lifetime Distribution of 10 kV SiC PiN Diodes by Physical Simulations
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2023 (English)In: Key Engineering Materials, ISSN 1013-9826, E-ISSN 1662-9795, Vol. 946, p. 119-124Article in journal (Refereed) Published
Abstract [en]

In this paper, Shockley-Read-Hall (SRH) lifetime depth profiles in the drift layer of 10 kV SiC PiN diodes are calculated after MeV proton implantation. It is assumed that the carbon vacancy will be the domination trap for charge carrier recombination and the SRH lifetime is calculated with defect parameters from the literature and proton-induced defect distributions deduced from SRIM calculations. The lifetime profiles are imported to Sentaurus TCAD and static and dynamic simulations using tailored lifetime profiles are carried out to study the electrical effect of proton implantation parameters. The results are compared to measurements, specializing on optimization of the trade off between on-state and turn-off losses, represented by the forward voltage drop, VT, and reverse recovery charge, Qrr, respectively. Both the simulated and measured IV characteristics show that increasing proton dose, or energy, has the effect on increasing forward voltage drop and on-state losses, while simultaneously, the localized SRH lifetime drop decreases the plasma level, increases the speed of recombination and decreases reverse recovery charge. Finally, TCAD simulations with different combinations of proton energies and fluences are used to optimize the trade-off between static and dynamic performances. Reverse recovery charge and forward voltage drops of these groups of diodes are plotted together, showing that a medium energy which induces the most defects in the depletion region relatively close to the anode gives the best dynamic performances, with a minimum cost of static performance.

National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:ri:diva-66636 (URN)10.4028/p-zo030o (DOI)
Available from: 2023-09-05 Created: 2023-09-05 Last updated: 2024-02-06Bibliographically approved
Wang, Q., Ramvall, P., Kumar, A., Öberg, O., Lim, J.-K., Krishna Murthy, H., . . . Bakowski, M. (2023). Wide bandgap semiconductor based innovative green technology for digital and industrial applications. In: : . Paper presented at 244th Electrochemical Society Meeting October 8-12, 2023 in Gothenburg Sweden..
Open this publication in new window or tab >>Wide bandgap semiconductor based innovative green technology for digital and industrial applications
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2023 (English)Conference paper, Oral presentation with published abstract (Other academic)
National Category
Computer and Information Sciences
Identifiers
urn:nbn:se:ri:diva-65524 (URN)
Conference
244th Electrochemical Society Meeting October 8-12, 2023 in Gothenburg Sweden.
Available from: 2023-06-22 Created: 2023-06-22 Last updated: 2024-05-22Bibliographically approved
Akbari, S., Kostov, K. S., Brinkfeldt, K., Adolfsson, E., Lim, J.-K., Andersson, D., . . . Salter, M. (2022). Ceramic Additive Manufacturing Potential for Power Electronics Packaging. IEEE Transactions on Components, Packaging, and Manufacturing Technology, 12(11), 1857-1866
Open this publication in new window or tab >>Ceramic Additive Manufacturing Potential for Power Electronics Packaging
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2022 (English)In: IEEE Transactions on Components, Packaging, and Manufacturing Technology, ISSN 2156-3950, E-ISSN 2156-3985, Vol. 12, no 11, p. 1857-1866Article in journal (Refereed) Published
Abstract [en]

Compared with silicon-based power devices, wide band gap (WBG) semiconductor devices operate at significantly higher power densities required in applications such as electric vehicles and more electric airplanes. This necessitates development of power electronics packages with enhanced thermal characteristics that fulfil the electrical insulation requirements. The present research investigates the feasibility of using ceramic additive manufacturing (AM), also known as three-dimensional (3D) printing, to address thermal and electrical requirements in packaging gallium nitride (GaN) based high-electron-mobility transistors (HEMTs). The goal is to exploit design freedom and manufacturing flexibility provided by ceramic AM to fabricate power device packages with a lower junction-to-ambient thermal resistance (<italic>R</italic>&#x03B8;JA). Ceramic AM also enables incorporation of intricate 3D features into the package structure in order to control the isolation distance between the package source and drain contact pads. Moreover, AM allows to fabricate different parts of the packaging assembly as a single structure to avoid high thermal resistance interfaces. For example, the ceramic package and the ceramic heatsink can be printed as a single part without any bonding layer. Thermal simulations under different thermal loading and cooling conditions show the improvement of thermal performance of the package fabricated by ceramic AM. If assisted by an efficient cooling strategy, the proposed package has the potential to reduce <italic>R</italic>&#x03B8;JA by up to 48%. The results of the preliminary efforts to fabricate the ceramic package by AM are presented, and the challenges that have to be overcome for further development of this manufacturing method are recognized and discussed. 

Place, publisher, year, edition, pages
Institute of Electrical and Electronics Engineers Inc., 2022
Keywords
Ceramic additive manufacturing, GaN HEMTs, isolation distance, power electronics packaging, thermal resistance, wide band gap semiconductors, 3D printers, Ceramic materials, Chip scale packages, Energy gap, Fabrication, Gallium nitride, High electron mobility transistors, III-V semiconductors, Industrial research, Thermal insulation, Ceramic additives, Ceramic package, Gallium nitride high-electron-mobility transistor, High electron-mobility transistors, Power devices, Silicon-based, Wide-band-gap semiconductor
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:ri:diva-62617 (URN)10.1109/TCPMT.2022.3224921 (DOI)2-s2.0-85144078339 (Scopus ID)
Note

This work supported by the Electronic Components and Systems for European Leadership (ECSEL) Joint Undertaking (JU) through the UltimateGaN Project and the European Union’s Horizon 2020 Research and Innovation Programunder Grant 826392.

Available from: 2023-01-20 Created: 2023-01-20 Last updated: 2024-04-05Bibliographically approved
Yuan, Z., Jacobs, K., Bakowski, M., Ranstad, P., Schöner, A., Reshanov, S., . . . Hallén, A. (2022). Localized Lifetime Control of 10 kV 4H-SiC PiN Diodes by MeV Proton Implantation. In: Materials Science Forum: . Paper presented at 13th European Conference on Silicon Carbide and Related Materials, ECSCRM 2021,Virtual, Online24 October 2021 through 28 October 2021 (pp. 442-446). Trans Tech Publications Ltd, 1062 MSF
Open this publication in new window or tab >>Localized Lifetime Control of 10 kV 4H-SiC PiN Diodes by MeV Proton Implantation
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2022 (English)In: Materials Science Forum, Trans Tech Publications Ltd , 2022, Vol. 1062 MSF, p. 442-446Conference paper, Published paper (Refereed)
Abstract [en]

In this paper, proton implantation with different combinations of MeV energies and doses from 2×109 to 1×1011 cm-2 is used to create defects in the drift region of 10 kV 4H-SiC PiN diodes to obtain a localized drop in the SRH lifetime. On-state and reverse recovery behaviors are measured to observe how MeV proton implantation influences these devices and values of reverse recovery charge Qrr are extracted. These measurements are carried out under different temperatures, showing that the reverse recovery behavior is sensitive to temperature due to the activation of incompletely ionized p-type acceptors. The results also show that increasing proton implantation energies and fluencies can have a strong effect on diodes and cause lower Qrr and switching losses, but also higher on-state voltage drop and forward conduction losses. The trade-off between static and dynamic performance is evaluated using Qrr and forward voltage drop. Higher fluencies, or energies, help to improve the turn-off performance, but at a cost of the static performance. © 2022 The Author(s).

Place, publisher, year, edition, pages
Trans Tech Publications Ltd, 2022
Keywords
Proton Implantation, Reverse Recovery, Shockley-Read-Hall (SRH) Lifetime, Switching Losses
National Category
Materials Engineering
Identifiers
urn:nbn:se:ri:diva-59860 (URN)10.4028/p-5po40a (DOI)2-s2.0-85134250220 (Scopus ID)9783035727609 (ISBN)
Conference
13th European Conference on Silicon Carbide and Related Materials, ECSCRM 2021,Virtual, Online24 October 2021 through 28 October 2021
Note

 Funding details: 2017-00646-9; Funding text 1: The Ion Technology Centre, ITC, in Uppsala, Sweden is acknowledged for proton implantations (contract 2017-00646-9).

Available from: 2022-08-02 Created: 2022-08-02 Last updated: 2024-02-06Bibliographically approved
Akbari, S., Kostov, K. S., Brinkfeldt, K., Bakowski, M. & Andersson, D. (2022). Low Inductive SiC Power Electronics Module with Flexible PCB Interconnections and 3D Printed Casing. In: 2022 IMAPS Nordic Conference on Microelectronics Packaging, NordPac 2022: . Paper presented at 2022 IMAPS Nordic Conference on Microelectronics Packaging, NordPac 2022, 12 June 2022 through 14 June 2022. Institute of Electrical and Electronics Engineers Inc.
Open this publication in new window or tab >>Low Inductive SiC Power Electronics Module with Flexible PCB Interconnections and 3D Printed Casing
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2022 (English)In: 2022 IMAPS Nordic Conference on Microelectronics Packaging, NordPac 2022, Institute of Electrical and Electronics Engineers Inc. , 2022Conference paper, Published paper (Refereed)
Abstract [en]

Silicon carbide (SiC) power devices are steadily increasing their market share in various power electronics applications. However, they require low-inductive packaging in order to realize their full potential. In this research, low-inductive layouts for half-bridge power modules, using a direct bonded copper (DBC) substrate, that are suitable for SiC power devices, were designed and tested. To reduce the negative effects of the switching transients on the gate voltage, flexible printed circuit boards (PCBs) were used to interconnect the gate and source pins of the module with the corresponding pads of the power chips. In addition, conductive springs were used as low inductive, solder-free contacts for the module power terminals. The module casing and lid were produced using additive manufacturing, also known as 3D printing, to create a compact design. It is shown that the inductance of this module is significantly lower than the commercially available modules.

Place, publisher, year, edition, pages
Institute of Electrical and Electronics Engineers Inc., 2022
Keywords
low inductive module, parasitic inductance, Power electronics packaging, SiC devices, Competition, Electric power system interconnection, Flexible electronics, Inductance, Integrated circuit interconnects, Microelectronics, Printed circuit boards, Silicon carbide, Flexible printed-circuit board, Market share, Parasitic inductances, Power electronics modules, Printed circuit board interconnections, Silicon carbide devices, Silicon carbide power, Silicon-carbide power devices, 3D printers
National Category
Physical Sciences
Identifiers
urn:nbn:se:ri:diva-60266 (URN)2-s2.0-85138492048 (Scopus ID)9789189711396 (ISBN)
Conference
2022 IMAPS Nordic Conference on Microelectronics Packaging, NordPac 2022, 12 June 2022 through 14 June 2022
Note

Funding details: 44163; Funding text 1: This work was performed under the project Low-Inductive SiC Module (LISM) that received funding from the Swedish energy agency Energimyndigheten with the grant agreement No 44163.

Available from: 2022-10-10 Created: 2022-10-10 Last updated: 2024-02-06Bibliographically approved
Jacobs, K., Bakowski, M., Ranstad, P. & Nee, H.-P. -. (2022). Static and Dynamic Performance of Charge-Carrier Lifetime-Tailored High-Voltage SiC p-i-n Diodes with Capacitively Assisted Switching. IEEE transactions on power electronics, 37(10), 12065-12079
Open this publication in new window or tab >>Static and Dynamic Performance of Charge-Carrier Lifetime-Tailored High-Voltage SiC p-i-n Diodes with Capacitively Assisted Switching
2022 (English)In: IEEE transactions on power electronics, ISSN 0885-8993, E-ISSN 1941-0107, Vol. 37, no 10, p. 12065-12079Article in journal (Refereed) Published
Abstract [en]

Recent advancements in the silicon carbide (SiC) power semiconductor technology offer improvements for high-power converters, where today silicon (Si) devices are still dominant. Bipolar SiC devices feature particularly good conduction capability while blocking high voltages. With expected advances in SiC material quality and processing technology, resulting in higher charge carrier lifetimes, methods for tailoring will be required. In this article, three differently optimized 10-kV SiC p-i-n diodes are compared regarding their switching and conduction performance in a 50-kHz LCC converter with a high output voltage. The converter topology features capacitively assisted switching, resulting in reduced switching losses for diodes with short reverse recovery tails. One diode group was subjected to a novel carrier lifetime tailoring method, involving simultaneous annihilation and generation of carbon vacancies. Another group was tailored via proton irradiation. Tradeoffs for the optimization of the diodes are highlighted. The analysis is supported by circuit simulations, device simulations, static measurements, switching waveform measurements, and calorimetric loss measurements. The results show a total rectifier loss reduction of 37%, compared to a state-of-the-art implementation with eight 1-kV Si diodes. The switching losses account for 3%-19% of the total losses, indicating a much higher possible operation frequency. 

Place, publisher, year, edition, pages
Institute of Electrical and Electronics Engineers Inc., 2022
Keywords
Charge-carrier lifetime, converters, power semiconductor diodes, rectifiers, resonant power conversion, semiconductor device testing, silicon carbide (SiC), Carbon, Carrier lifetime, Circuit simulation, Economic and social effects, Electric rectifiers, Proton irradiation, Rectifying circuits, Semiconducting silicon, Semiconductor device manufacture, Switching, Wide band gap semiconductors, Charge carrier lifetime, Converter, High-voltages, Loss measurement, PiN diode, Rectifier, Static and dynamic performance, Switching loss, Silicon carbide
National Category
Engineering and Technology
Identifiers
urn:nbn:se:ri:diva-60608 (URN)10.1109/TPEL.2022.3172666 (DOI)2-s2.0-85132537179 (Scopus ID)
Available from: 2022-10-14 Created: 2022-10-14 Last updated: 2024-02-06Bibliographically approved
Bakowski, M. & Gisslander, U. (2022). Theoretical Benchmarking of Vertical GaN Devices. In: International Conference on Electrical, Computer, Communications and Mechatronics Engineering, ICECCME 2022: . Paper presented at 2022 International Conference on Electrical, Computer, Communications and Mechatronics Engineering, ICECCME 2022, 16 November 2022 through 18 November 2022. Institute of Electrical and Electronics Engineers Inc.
Open this publication in new window or tab >>Theoretical Benchmarking of Vertical GaN Devices
2022 (English)In: International Conference on Electrical, Computer, Communications and Mechatronics Engineering, ICECCME 2022, Institute of Electrical and Electronics Engineers Inc. , 2022Conference paper, Published paper (Refereed)
Abstract [en]

In this paper theoretical benchmarking of semi-vertical and vertical gallium nitride (GaN) MOSFETs with rated voltage of 1.2 kV to 3.3 kV is performed against corresponding silicon carbide (SiC) devices. Specific design features and technology requirements for realization of high voltage vertical GaN MOSFETs are discussed and implemented in simulated structures. The main findings are that a) specific on-resistance of vertical GaN devices is expected to be 75% and 40% of that for 1.2 kV and 3.3 kV SiC MOSFETs, respectively, b) semi-vertical GaN do not offer any advantage over SiC MOSFETs for medium and high voltage devices (>1.0 kV), and c) vertical GaN has largest potential advantage for high and ultra-high voltage devices (>2.0 kV).

Place, publisher, year, edition, pages
Institute of Electrical and Electronics Engineers Inc., 2022
Keywords
benchmarking with SiC, device modeling, GaN, specific on-resistance, TCAD, vertical MOSFET, WBG devices, Benchmarking, Electronic design automation, III-V semiconductors, MOSFET devices, Silicon carbide, Wide band gap semiconductors, Benchmarking with silicon carbide, Device modelling, High voltage devices, MOSFETs, Rated voltages, Silicon carbide MOSFETs, Specific-on-resistance, Vertical MOSFETs, WBG device, Gallium nitride
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:ri:diva-64011 (URN)10.1109/ICECCME55909.2022.9987919 (DOI)2-s2.0-85146423232 (Scopus ID)9781665470957 (ISBN)
Conference
2022 International Conference on Electrical, Computer, Communications and Mechatronics Engineering, ICECCME 2022, 16 November 2022 through 18 November 2022
Note

Funding details: Electronic Components and Systems for European Leadership, ECSEL, 826392; Funding text 1: This project has received funding from the ECSEL Joint Undertaking (JU) under grant agreement No 826392 (UltimateGaN).

Available from: 2023-02-22 Created: 2023-02-22 Last updated: 2024-02-06Bibliographically approved
Sadik, D., Colmenares, J., Lim, J.-K., Bakowski, M. & Nee, H. P. (2020). Comparison of Thermal Stress during Short-Circuit in Different Types of 1.2 kV SiC Transistors Based on Experiments and Simulations. IEEE Transactions on Industrial Electronics, 897, 595-598
Open this publication in new window or tab >>Comparison of Thermal Stress during Short-Circuit in Different Types of 1.2 kV SiC Transistors Based on Experiments and Simulations
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2020 (English)In: IEEE Transactions on Industrial Electronics, ISSN 0278-0046, E-ISSN 1557-9948, Vol. 897, p. 595-598Article in journal (Refereed) Published
Abstract [en]

The temperature evolution during a short-circuit fault in the dies of three different Silicon Carbide 1200-V power devices is presented. Transient electro-thermal simulations were performed based on the reconstructed structure of commercially available devices. The simulations reveal the location of the hottest point in each device. The nonisothermal electrical analysis supports the necessity to turn OFF short-circuit events rapidly to protect the immunity of the device after a fault. The analysis also reveal differences in delay required to turn OFF devices depending on their type. A thorough analysis of the temperature rise in the die of the SiC MOSFET device is also presented, where the maximum temperature with regards to different fault cases and circuit characteristics is presented. The impact of the gate resistance, circuit inductance, detection time, drain-source voltage, and gate-source voltage are considered.

Keywords
Silicon carbide, MOSFET, JFETs, Circuit faults, Temperature, Integrated circuit modeling, Performance evaluation, Silicon Carbide (SiC), JFET, BJT, Reliability, Device Simuation, Short-circuit currents, Failure Analysis
National Category
Natural Sciences
Identifiers
urn:nbn:se:ri:diva-44538 (URN)10.1109/TIE.2020.2972442 (DOI)2-s2.0-85020002693 (Scopus ID)
Available from: 2020-03-17 Created: 2020-03-17 Last updated: 2024-04-08Bibliographically approved
Zhang, Y., Nee, H. P., Hammam, T., Belov, I., Ranstad, P. & Bakowski, M. (2019). Multiphysics Characterization of a Novel SiC Power Module. IEEE Transactions on Components, Packaging, and Manufacturing Technology, 9(3), 489-501
Open this publication in new window or tab >>Multiphysics Characterization of a Novel SiC Power Module
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2019 (English)In: IEEE Transactions on Components, Packaging, and Manufacturing Technology, ISSN 2156-3950, E-ISSN 2156-3985, Vol. 9, no 3, p. 489-501Article in journal (Refereed) Published
Abstract [en]

This paper proposes a novel power module concept specially designed for highly reliable silicon carbide power devices for medium- and high-power applications. The concept consists of two clamped structures: 1) a press-pack power stage accommodating silicon carbide power switch dies, and 2) perpendicularly clamped press-pack heatsinks, in which, the heatsinks are in contact with electrically insulated case plates of the power stage. The concept enables bondless package with symmetric double-sided cooling of the dies and allows for an order of magnitude higher clamping force on the heatsinks than what can be applied on the dies. The concept has been evaluated in a first demonstrator (half-bridge configuration with ten paralleled silicon carbide dies in each position). Experimental methodologies, setups, and procedures have been presented. The commutation loop inductance is approximately 9 nH at 78 kHz. The junction-to-case thermal resistance is approximately 0.028 K/W. Furthermore, a simplified 3D finite element thermomechanical model representing the center unit of the demonstrator, has been established for the purpose of future optimization. The accuracy of the simulated temperatures is within 4 % compared to the measurements. Finally, a 3D thermomechanical stress distribution map has been obtained for the simplified model of the demonstrator.

Keywords
Force, Clamps, Insulation, Silicon carbide, Heat sinks, Friction, Thermal resistance, Computational fluid dynamics, electromagnetic analysis, finite element analysis, inductance, measurement techniques, power electronics, power electronics packaging, press-pack technology, thermomechanical simulation.
National Category
Natural Sciences
Identifiers
urn:nbn:se:ri:diva-35247 (URN)10.1109/TCPMT.2018.2873231 (DOI)2-s2.0-85054397136 (Scopus ID)
Available from: 2018-10-15 Created: 2018-10-15 Last updated: 2024-02-06Bibliographically approved
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Identifiers
ORCID iD: ORCID iD iconorcid.org/0000-0002-9512-2689

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